[v5,24/30] LoongArch: KVM: Implement handle mmio exception

Message ID	20230407020003.3651096-25-zhaotianrui@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Tianrui Zhao <zhaotianrui@loongson.cn> To: Paolo Bonzini <pbonzini@redhat.com> Cc: Huacai Chen <chenhuacai@kernel.org>, WANG Xuerui <kernel@xen0n.name>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Jens Axboe <axboe@kernel.dk>, Mark Brown <broonie@kernel.org>, Alex Deucher <alexander.deucher@amd.com>, Oliver Upton <oliver.upton@linux.dev>, maobibo@loongson.cn, Xi Ruoyao <xry111@xry111.site>, zhaotianrui@loongson.cn Subject: [PATCH v5 24/30] LoongArch: KVM: Implement handle mmio exception Date: Fri, 7 Apr 2023 09:59:57 +0800 Message-Id: <20230407020003.3651096-25-zhaotianrui@loongson.cn> In-Reply-To: <20230407020003.3651096-1-zhaotianrui@loongson.cn> References: <20230407020003.3651096-1-zhaotianrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add KVM LoongArch support \| expand [v5,00/30] Add KVM LoongArch support [v5,01/30] LoongArch: KVM: Add kvm related header files [v5,02/30] LoongArch: KVM: Implement kvm module related interface [v5,03/30] LoongArch: KVM: Implement kvm hardware enable, disable interface [v5,04/30] LoongArch: KVM: Implement VM related functions [v5,05/30] LoongArch: KVM: Add vcpu related header files [v5,06/30] LoongArch: KVM: Implement vcpu create and destroy interface [v5,07/30] LoongArch: KVM: Implement vcpu run interface [v5,08/30] LoongArch: KVM: Implement vcpu handle exit interface [v5,09/30] LoongArch: KVM: Implement vcpu get, vcpu set registers [v5,10/30] LoongArch: KVM: Implement vcpu ENABLE_CAP ioctl interface [v5,11/30] LoongArch: KVM: Implement fpu related operations for vcpu [v5,12/30] LoongArch: KVM: Implement vcpu interrupt operations [v5,13/30] LoongArch: KVM: Implement misc vcpu related interfaces [v5,14/30] LoongArch: KVM: Implement vcpu load and vcpu put operations [v5,15/30] LoongArch: KVM: Implement vcpu status description [v5,16/30] LoongArch: KVM: Implement update VM id function [v5,17/30] LoongArch: KVM: Implement virtual machine tlb operations [v5,18/30] LoongArch: KVM: Implement vcpu timer operations [v5,19/30] LoongArch: KVM: Implement kvm mmu operations [v5,20/30] LoongArch: KVM: Implement handle csr excption [v5,21/30] LoongArch: KVM: Implement handle iocsr exception [v5,22/30] LoongArch: KVM: Implement handle idle exception [v5,23/30] LoongArch: KVM: Implement handle gspr exception [v5,24/30] LoongArch: KVM: Implement handle mmio exception [v5,25/30] LoongArch: KVM: Implement handle fpu exception [v5,26/30] LoongArch: KVM: Implement kvm exception vector [v5,27/30] LoongArch: KVM: Implement vcpu world switch [v5,28/30] LoongArch: KVM: Implement probe virtualization when loongarch cpu init [v5,29/30] LoongArch: KVM: Enable kvm config and add the makefile [v5,30/30] LoongArch: KVM: Supplement kvm document about loongarch-specific part

diff --git a/arch/loongarch/kvm/exit.c b/arch/loongarch/kvm/exit.c index 717ef0133..0daf18242 100644 --- a/arch/loongarch/kvm/exit.c +++ b/arch/loongarch/kvm/exit.c @@ -211,6 +211,265 @@ int _kvm_emu_idle(struct kvm_vcpu *vcpu) return EMULATE_DONE; } +int _kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst) +{ + struct kvm_run *run = vcpu->run; + unsigned int rd, op8, opcode; + unsigned long rd_val = 0; + void *data = run->mmio.data; + unsigned long curr_pc; + int ret; + + /* + * Update PC and hold onto current PC in case there is + * an error and we want to rollback the PC + */ + curr_pc = vcpu->arch.pc; + update_pc(&vcpu->arch); + + op8 = (inst.word >> 24) & 0xff; + run->mmio.phys_addr = vcpu->arch.badv; + ret = EMULATE_DO_MMIO; + if (op8 < 0x28) { + /* stptrw/d process */ + rd = inst.reg2i14_format.rd; + opcode = inst.reg2i14_format.opcode; + + switch (opcode) { + case stptrd_op: + run->mmio.len = 8; + *(unsigned long *)data = vcpu->arch.gprs[rd]; + break; + case stptrw_op: + run->mmio.len = 4; + *(unsigned int *)data = vcpu->arch.gprs[rd]; + break; + default: + ret = EMULATE_FAIL; + break; + } + } else if (op8 < 0x30) { + /* st.b/h/w/d process */ + rd = inst.reg2i12_format.rd; + opcode = inst.reg2i12_format.opcode; + rd_val = vcpu->arch.gprs[rd]; + + switch (opcode) { + case std_op: + run->mmio.len = 8; + *(unsigned long *)data = rd_val; + break; + case stw_op: + run->mmio.len = 4; + *(unsigned int *)data = rd_val; + break; + case sth_op: + run->mmio.len = 2; + *(unsigned short *)data = rd_val; + break; + case stb_op: + run->mmio.len = 1; + *(unsigned char *)data = rd_val; + break; + default: + ret = EMULATE_FAIL; + break; + } + } else if (op8 == 0x38) { + /* stxb/h/w/d process */ + rd = inst.reg3_format.rd; + opcode = inst.reg3_format.opcode; + + switch (opcode) { + case stxb_op: + run->mmio.len = 1; + *(unsigned char *)data = vcpu->arch.gprs[rd]; + break; + case stxh_op: + run->mmio.len = 2; + *(unsigned short *)data = vcpu->arch.gprs[rd]; + break; + case stxw_op: + run->mmio.len = 4; + *(unsigned int *)data = vcpu->arch.gprs[rd]; + break; + case stxd_op: + run->mmio.len = 8; + *(unsigned long *)data = vcpu->arch.gprs[rd]; + break; + default: + ret = EMULATE_FAIL; + break; + } + } else + ret = EMULATE_FAIL; + + if (ret == EMULATE_DO_MMIO) { + run->mmio.is_write = 1; + vcpu->mmio_needed = 1; + vcpu->mmio_is_write = 1; + } else { + vcpu->arch.pc = curr_pc; + kvm_err("Write not supporded inst=0x%08x @%lx BadVaddr:%#lx\n", + inst.word, vcpu->arch.pc, vcpu->arch.badv); + kvm_arch_vcpu_dump_regs(vcpu); + /* Rollback PC if emulation was unsuccessful */ + } + + return ret; +} + +int _kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst) +{ + unsigned int op8, opcode, rd; + struct kvm_run *run = vcpu->run; + int ret; + + run->mmio.phys_addr = vcpu->arch.badv; + vcpu->mmio_needed = 2; /* signed */ + op8 = (inst.word >> 24) & 0xff; + ret = EMULATE_DO_MMIO; + + if (op8 < 0x28) { + /* ldptr.w/d process */ + rd = inst.reg2i14_format.rd; + opcode = inst.reg2i14_format.opcode; + + switch (opcode) { + case ldptrd_op: + run->mmio.len = 8; + break; + case ldptrw_op: + run->mmio.len = 4; + break; + default: + break; + } + } else if (op8 < 0x2f) { + /* ld.b/h/w/d, ld.bu/hu/wu process */ + rd = inst.reg2i12_format.rd; + opcode = inst.reg2i12_format.opcode; + + switch (opcode) { + case ldd_op: + run->mmio.len = 8; + break; + case ldwu_op: + vcpu->mmio_needed = 1; /* unsigned */ + run->mmio.len = 4; + break; + case ldw_op: + run->mmio.len = 4; + break; + case ldhu_op: + vcpu->mmio_needed = 1; /* unsigned */ + run->mmio.len = 2; + break; + case ldh_op: + run->mmio.len = 2; + break; + case ldbu_op: + vcpu->mmio_needed = 1; /* unsigned */ + run->mmio.len = 1; + break; + case ldb_op: + run->mmio.len = 1; + break; + default: + ret = EMULATE_FAIL; + break; + } + } else if (op8 == 0x38) { + /* ldxb/h/w/d, ldxb/h/wu, ldgtb/h/w/d, ldleb/h/w/d process */ + rd = inst.reg3_format.rd; + opcode = inst.reg3_format.opcode; + + switch (opcode) { + case ldxb_op: + run->mmio.len = 1; + break; + case ldxbu_op: + run->mmio.len = 1; + vcpu->mmio_needed = 1; /* unsigned */ + break; + case ldxh_op: + run->mmio.len = 2; + break; + case ldxhu_op: + run->mmio.len = 2; + vcpu->mmio_needed = 1; /* unsigned */ + break; + case ldxw_op: + run->mmio.len = 4; + break; + case ldxwu_op: + run->mmio.len = 4; + vcpu->mmio_needed = 1; /* unsigned */ + break; + case ldxd_op: + run->mmio.len = 8; + break; + default: + ret = EMULATE_FAIL; + break; + } + } else + ret = EMULATE_FAIL; + + if (ret == EMULATE_DO_MMIO) { + /* Set for _kvm_complete_mmio_read use */ + vcpu->arch.io_gpr = rd; + run->mmio.is_write = 0; + vcpu->mmio_is_write = 0; + } else { + kvm_err("Load not supporded inst=0x%08x @%lx BadVaddr:%#lx\n", + inst.word, vcpu->arch.pc, vcpu->arch.badv); + kvm_arch_vcpu_dump_regs(vcpu); + vcpu->mmio_needed = 0; + } + return ret; +} + +int _kvm_complete_mmio_read(struct kvm_vcpu *vcpu, struct kvm_run *run) +{ + unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; + enum emulation_result er = EMULATE_DONE; + + /* update with new PC */ + update_pc(&vcpu->arch); + switch (run->mmio.len) { + case 8: + *gpr = *(s64 *)run->mmio.data; + break; + case 4: + if (vcpu->mmio_needed == 2) + *gpr = *(int *)run->mmio.data; + else + *gpr = *(unsigned int *)run->mmio.data; + break; + case 2: + if (vcpu->mmio_needed == 2) + *gpr = *(short *) run->mmio.data; + else + *gpr = *(unsigned short *)run->mmio.data; + + break; + case 1: + if (vcpu->mmio_needed == 2) + *gpr = *(char *) run->mmio.data; + else + *gpr = *(unsigned char *) run->mmio.data; + break; + default: + kvm_err("Bad MMIO length: %d,addr is 0x%lx", + run->mmio.len, vcpu->arch.badv); + er = EMULATE_FAIL; + break; + } + + return er; +} + static int _kvm_trap_handle_gspr(struct kvm_vcpu *vcpu) { enum emulation_result er = EMULATE_DONE; @@ -325,3 +584,52 @@ static int _kvm_handle_gspr(struct kvm_vcpu *vcpu) } return ret; } + +static int _kvm_handle_mmu_fault(struct kvm_vcpu *vcpu, bool write) +{ + struct kvm_run *run = vcpu->run; + unsigned long badv = vcpu->arch.badv; + larch_inst inst; + enum emulation_result er = EMULATE_DONE; + int ret; + + ret = kvm_handle_mm_fault(vcpu, badv, write); + if (ret) { + /* Treat as MMIO */ + inst.word = vcpu->arch.badi; + if (write) { + er = _kvm_emu_mmio_write(vcpu, inst); + } else { + /* A code fetch fault doesn't count as an MMIO */ + if (kvm_is_ifetch_fault(&vcpu->arch)) { + kvm_err("%s ifetch error addr:%lx\n", __func__, badv); + run->exit_reason = KVM_EXIT_INTERNAL_ERROR; + return RESUME_HOST; + } + + er = _kvm_emu_mmio_read(vcpu, inst); + } + } + + if (er == EMULATE_DONE) { + ret = RESUME_GUEST; + } else if (er == EMULATE_DO_MMIO) { + run->exit_reason = KVM_EXIT_MMIO; + ret = RESUME_HOST; + } else { + run->exit_reason = KVM_EXIT_INTERNAL_ERROR; + ret = RESUME_HOST; + } + + return ret; +} + +static int _kvm_handle_write_fault(struct kvm_vcpu *vcpu) +{ + return _kvm_handle_mmu_fault(vcpu, true); +} + +static int _kvm_handle_read_fault(struct kvm_vcpu *vcpu) +{ + return _kvm_handle_mmu_fault(vcpu, false); +}

[v5,24/30] LoongArch: KVM: Implement handle mmio exception

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