| Message ID | 20230428144757.57530-6-lawrence.hunter@codethink.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V vector cryptographic instruction set support | expand |
On 2023/4/28 22:47, Lawrence Hunter wrote: > From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > > Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions > and into the corresponding macros. This enables the functions to be > reused in proceeding commits without check duplication. > > Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++-------------- > 1 file changed, 12 insertions(+), 16 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 2660dda42be..21731b784ec 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -1183,9 +1183,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, > gen_helper_gvec_4_ptr *fn) > { > TCGLabel *over = gen_new_label(); > - if (!opivv_check(s, a)) { > - return false; > - } > > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); > > @@ -1218,6 +1215,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ > gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ > }; \ > + if (!opivv_check(s, a)) { \ > + return false; \ > + } \ > return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ > } > > @@ -1276,10 +1276,6 @@ static inline bool > do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, > gen_helper_opivx *fn) > { > - if (!opivx_check(s, a)) { > - return false; > - } > - > if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { > TCGv_i64 src1 = tcg_temp_new_i64(); > > @@ -1301,6 +1297,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ > gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ > }; \ > + if (!opivx_check(s, a)) { \ > + return false; \ > + } \ > return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ > } > > @@ -1432,10 +1431,6 @@ static inline bool > do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, > gen_helper_opivx *fn, imm_mode_t imm_mode) > { > - if (!opivx_check(s, a)) { > - return false; > - } > - > if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { > gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), > extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); > @@ -1453,6 +1448,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ > gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ > }; \ > + if (!opivx_check(s, a)) { \ > + return false; \ > + } \ > return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ > fns[s->sew], IMM_MODE); \ > } > @@ -1775,10 +1773,6 @@ static inline bool > do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, > gen_helper_opivx *fn) > { > - if (!opivx_check(s, a)) { > - return false; > - } > - > if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { > TCGv_i32 src1 = tcg_temp_new_i32(); > > @@ -1800,7 +1794,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ > gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ > }; \ > - \ > + if (!opivx_check(s, a)) { \ > + return false; \ > + } \ > return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ > } >
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 2660dda42be..21731b784ec 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1183,9 +1183,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, gen_helper_gvec_4_ptr *fn) { TCGLabel *over = gen_new_label(); - if (!opivv_check(s, a)) { - return false; - } tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); @@ -1218,6 +1215,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivv_check(s, a)) { \ + return false; \ + } \ return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } @@ -1276,10 +1276,6 @@ static inline bool do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i64 src1 = tcg_temp_new_i64(); @@ -1301,6 +1297,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } @@ -1432,10 +1431,6 @@ static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, gen_helper_opivx *fn, imm_mode_t imm_mode) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); @@ -1453,6 +1448,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ fns[s->sew], IMM_MODE); \ } @@ -1775,10 +1773,6 @@ static inline bool do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i32 src1 = tcg_temp_new_i32(); @@ -1800,7 +1794,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ - \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ }