@@ -232,4 +232,10 @@ static __always_inline bool guest_pv_has(struct kvm_vcpu *vcpu,
return vcpu->arch.pv_cpuid.features & (1u << kvm_feature);
}
+static __always_inline bool kvm_cet_kernel_shstk_supported(void)
+{
+ return !IS_ENABLED(CONFIG_KVM_INTEL) &&
+ kvm_cpu_cap_has(X86_FEATURE_SHSTK);
+}
+
#endif
@@ -670,6 +670,18 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
MSR_IA32_PL3_SSP, MSR_TYPE_RW);
+ nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
+ MSR_IA32_PL0_SSP, MSR_TYPE_RW);
+
+ nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
+ MSR_IA32_PL1_SSP, MSR_TYPE_RW);
+
+ nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
+ MSR_IA32_PL2_SSP, MSR_TYPE_RW);
+
+ nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
+ MSR_IA32_INT_SSP_TAB, MSR_TYPE_RW);
+
kvm_vcpu_unmap(vcpu, &vmx->nested.msr_bitmap_map, false);
vmx->nested.force_msr_bitmap_recalc = false;
@@ -713,6 +713,9 @@ static bool is_valid_passthrough_msr(u32 msr)
case MSR_IA32_PL3_SSP:
case MSR_IA32_S_CET:
return true;
+ case MSR_IA32_PL0_SSP ... MSR_IA32_PL2_SSP:
+ case MSR_IA32_INT_SSP_TAB:
+ return true;
}
r = possible_passthrough_msr_slot(msr) != -ENOENT;
@@ -2101,12 +2104,16 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_S_CET:
case MSR_IA32_PL3_SSP:
case MSR_KVM_GUEST_SSP:
+ case MSR_IA32_PL0_SSP ... MSR_IA32_PL2_SSP:
+ case MSR_IA32_INT_SSP_TAB:
if (!kvm_cet_is_msr_accessible(vcpu, msr_info))
return 1;
if (msr_info->index == MSR_KVM_GUEST_SSP) {
msr_info->data = vmcs_readl(GUEST_SSP);
} else if (msr_info->index == MSR_IA32_S_CET) {
msr_info->data = vmcs_readl(GUEST_S_CET);
+ } else if (msr_info->index == MSR_IA32_INT_SSP_TAB) {
+ msr_info->data = vmcs_readl(GUEST_INTR_SSP_TABLE);
} else {
kvm_get_xsave_msr(msr_info);
}
@@ -2427,6 +2434,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_IA32_S_CET:
case MSR_IA32_PL3_SSP:
case MSR_KVM_GUEST_SSP:
+ case MSR_IA32_PL0_SSP ... MSR_IA32_PL2_SSP:
+ case MSR_IA32_INT_SSP_TAB:
if (!kvm_cet_is_msr_accessible(vcpu, msr_info))
return 1;
if (is_noncanonical_address(data, vcpu))
@@ -2440,6 +2449,8 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
vmcs_writel(GUEST_SSP, data);
} else if (msr_index == MSR_IA32_S_CET) {
vmcs_writel(GUEST_S_CET, data);
+ } else if (msr_index == MSR_IA32_INT_SSP_TAB) {
+ vmcs_writel(GUEST_INTR_SSP_TABLE, data);
} else {
kvm_set_xsave_msr(msr_info);
}
@@ -7764,6 +7775,17 @@ static void vmx_update_intercept_for_cet_msr(struct kvm_vcpu *vcpu)
*/
incpt = !guest_cpuid_has(vcpu, X86_FEATURE_IBT);
vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, incpt);
+
+ /*
+ * Supervisor shadow stack is not supported in VMX now, intercept all
+ * related MSRs.
+ */
+ incpt = !kvm_cet_kernel_shstk_supported();
+
+ vmx_set_intercept_for_msr(vcpu, MSR_IA32_INT_SSP_TAB, MSR_TYPE_RW, incpt);
+ vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, incpt);
+ vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, incpt);
+ vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, incpt);
}
static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
@@ -7834,7 +7856,8 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
/* Refresh #PF interception to account for MAXPHYADDR changes. */
vmx_update_exception_bitmap(vcpu);
- if (kvm_cet_user_supported() || kvm_cpu_cap_has(X86_FEATURE_IBT))
+ if (kvm_cet_user_supported() || kvm_cpu_cap_has(X86_FEATURE_IBT) ||
+ kvm_cpu_cap_has(X86_FEATURE_SHSTK))
vmx_update_intercept_for_cet_msr(vcpu);
}
@@ -1472,6 +1472,8 @@ static const u32 msrs_to_save_base[] = {
MSR_IA32_XSS,
MSR_IA32_U_CET, MSR_IA32_PL3_SSP, MSR_KVM_GUEST_SSP,
MSR_IA32_S_CET,
+ MSR_IA32_PL0_SSP, MSR_IA32_PL1_SSP, MSR_IA32_PL2_SSP,
+ MSR_IA32_INT_SSP_TAB,
};
static const u32 msrs_to_save_pmu[] = {
@@ -13653,8 +13655,11 @@ EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
bool kvm_cet_is_msr_accessible(struct kvm_vcpu *vcpu, struct msr_data *msr)
{
+ u64 mask;
+
if (!kvm_cet_user_supported() &&
- !kvm_cpu_cap_has(X86_FEATURE_IBT))
+ !(kvm_cpu_cap_has(X86_FEATURE_IBT) ||
+ kvm_cpu_cap_has(X86_FEATURE_SHSTK)))
return false;
if (msr->host_initiated)
@@ -13668,14 +13673,24 @@ bool kvm_cet_is_msr_accessible(struct kvm_vcpu *vcpu, struct msr_data *msr)
if (msr->index == MSR_KVM_GUEST_SSP)
return false;
+ if (msr->index == MSR_IA32_U_CET)
+ return true;
+
if (msr->index == MSR_IA32_S_CET)
- return guest_cpuid_has(vcpu, X86_FEATURE_IBT);
+ return guest_cpuid_has(vcpu, X86_FEATURE_IBT) ||
+ kvm_cet_kernel_shstk_supported();
+
+ if (msr->index == MSR_IA32_INT_SSP_TAB)
+ return guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) &&
+ kvm_cet_kernel_shstk_supported();
if (msr->index == MSR_IA32_PL3_SSP &&
!guest_cpuid_has(vcpu, X86_FEATURE_SHSTK))
return false;
- return true;
+ mask = (msr->index == MSR_IA32_PL3_SSP) ? XFEATURE_MASK_CET_USER :
+ XFEATURE_MASK_CET_KERNEL;
+ return !!(kvm_caps.supported_xss & mask);
}
EXPORT_SYMBOL_GPL(kvm_cet_is_msr_accessible);
Add MSR access interfaces for supervisor shadow stack, i.e., MSR_IA32_PL{0,1,2} and MSR_IA32_INT_SSP_TAB, meanwhile pass through them to {L1,L2} guests when {L0,L1} KVM supports supervisor shadow stack. Note, currently supervisor shadow stack is not supported on Intel platforms, i.e., VMX always clears CPUID(EAX=07H,ECX=1):EDX[bit 18]. The main purpose of this patch is to facilitate AMD folks to enable supervisor shadow stack for their platforms. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> --- arch/x86/kvm/cpuid.h | 6 ++++++ arch/x86/kvm/vmx/nested.c | 12 ++++++++++++ arch/x86/kvm/vmx/vmx.c | 25 ++++++++++++++++++++++++- arch/x86/kvm/x86.c | 21 ++++++++++++++++++--- 4 files changed, 60 insertions(+), 4 deletions(-)