diff mbox series

[v10,02/59] arm64: Add missing Set/Way CMO encodings

Message ID	20230515173103.1017669-3-maz@kernel.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Marc Zyngier <maz@kernel.org> To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Alexandru Elisei <alexandru.elisei@arm.com>, Andre Przywara <andre.przywara@arm.com>, Chase Conklin <chase.conklin@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>, Darren Hart <darren@os.amperecomputing.com>, Jintack Lim <jintack@cs.columbia.edu>, Russell King <rmk+kernel@armlinux.org.uk>, Miguel Luis <miguel.luis@oracle.com>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Oliver Upton <oliver.upton@linux.dev>, Zenghui Yu <yuzenghui@huawei.com> Subject: [PATCH v10 02/59] arm64: Add missing Set/Way CMO encodings Date: Mon, 15 May 2023 18:30:06 +0100 Message-Id: <20230515173103.1017669-3-maz@kernel.org> In-Reply-To: <20230515173103.1017669-1-maz@kernel.org> References: <20230515173103.1017669-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	KVM: arm64: ARMv8.3/8.4 Nested Virtualization support \| expand [v10,00/59] KVM: arm64: ARMv8.3/8.4 Nested Virtualization support [v10,01/59] KVM: arm64: Move VTCR_EL2 into struct s2_mmu [v10,02/59] arm64: Add missing Set/Way CMO encodings [v10,03/59] arm64: Add missing VA CMO encodings [v10,04/59] arm64: Add missing ERXMISCx_EL1 encodings [v10,05/59] arm64: Add missing DC ZVA/GVA/GZVA encodings [v10,06/59] arm64: Add TLBI operation encodings [v10,07/59] arm64: Add AT operation encodings [v10,08/59] KVM: arm64: Add missing HCR_EL2 trap bits [v10,09/59] KVM: arm64: nv: Add trap forwarding infrastructure [v10,10/59] KVM: arm64: nv: Add trap forwarding for HCR_EL2 [v10,11/59] KVM: arm64: nv: Expose FEAT_EVT to nested guests [v10,12/59] KVM: arm64: nv: Add trap forwarding for MDCR_EL2 [v10,13/59] KVM: arm64: nv: Add trap forwarding for CNTHCTL_EL2 [v10,14/59] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers [v10,15/59] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() [v10,16/59] KVM: arm64: nv: Handle SPSR_EL2 specially [v10,17/59] KVM: arm64: nv: Handle HCR_EL2.E2H specially [v10,18/59] KVM: arm64: nv: Save/Restore vEL2 sysregs [v10,19/59] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 [v10,20/59] KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2 [v10,21/59] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting [v10,22/59] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings [v10,23/59] KVM: arm64: nv: Respect virtual HCR_EL2.{NV,TSC) settings [v10,24/59] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization [v10,25/59] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures [v10,26/59] KVM: arm64: nv: Implement nested Stage-2 page table walk logic [v10,27/59] KVM: arm64: nv: Handle shadow stage 2 page faults [v10,28/59] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's [v10,29/59] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables [v10,30/59] KVM: arm64: nv: Set a handler for the system instruction traps [v10,31/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 [v10,32/59] KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2 [v10,33/59] KVM: arm64: nv: Fold guest's HCR_EL2 configuration into the host's [v10,34/59] KVM: arm64: nv: Hide RAS from nested guests [v10,35/59] KVM: arm64: nv: Add handling of EL2-specific timer registers [v10,36/59] KVM: arm64: nv: Load timer before the GIC [v10,37/59] KVM: arm64: nv: Nested GICv3 Support [v10,38/59] KVM: arm64: nv: Don't load the GICv4 context on entering a nested guest [v10,39/59] KVM: arm64: nv: vgic: Emulate the HW bit in software [v10,40/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ [v10,41/59] KVM: arm64: nv: Implement maintenance interrupt forwarding [v10,42/59] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery [v10,43/59] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT [v10,44/59] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation [v10,45/59] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information [v10,46/59] KVM: arm64: nv: Tag shadow S2 entries with nested level [v10,47/59] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets [v10,48/59] KVM: arm64: nv: Map VNCR-capable registers to a separate page [v10,49/59] KVM: arm64: nv: Move nested vgic state into the sysreg file [v10,50/59] KVM: arm64: Add FEAT_NV2 cpu feature [v10,51/59] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 [v10,52/59] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup [v10,53/59] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state [v10,54/59] KVM: arm64: nv: Allocate VNCR page when required [v10,55/59] KVM: arm64: nv: Enable ARMv8.4-NV support [v10,56/59] KVM: arm64: nv: Fast-track 'InHost' exception returns [v10,57/59] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests [v10,58/59] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers [v10,59/59] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on

Commit Message

Marc Zyngier May 15, 2023, 5:30 p.m. UTC

Add the missing Set/Way CMOs that apply to tagged memory.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a43f21559c3e..108663aebccb 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -115,8 +115,14 @@ 
 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
 
 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
+#define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
+#define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
+#define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
+#define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
+#define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
+#define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
 
 /*
  * Automatically generated definitions for system registers, the