[-next,v20,18/26] riscv: kvm: Add V extension to KVM ISA

Message ID	20230518161949.11203-19-andy.chiu@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: [PATCH -next v20 18/26] riscv: kvm: Add V extension to KVM ISA Date: Thu, 18 May 2023 16:19:41 +0000 Message-Id: <20230518161949.11203-19-andy.chiu@sifive.com> In-Reply-To: <20230518161949.11203-1-andy.chiu@sifive.com> References: <20230518161949.11203-1-andy.chiu@sifive.com> Precedence: bulk
Series	riscv: Add vector ISA support \| expand [-next,v20,00/26] riscv: Add vector ISA support [-next,v20,01/26] riscv: Rename __switch_to_aux() -> fpu [-next,v20,02/26] riscv: Extending cpufeature.c to detect V-extension [-next,v20,03/26] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 [-next,v20,04/26] riscv: Add new csr defines related to vector extension [-next,v20,05/26] riscv: Clear vector regfile on bootup [-next,v20,06/26] riscv: Disable Vector Instructions for kernel itself [-next,v20,07/26] riscv: Introduce Vector enable/disable helpers [-next,v20,08/26] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v20,09/26] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v20,10/26] riscv: Add task switch support for vector [-next,v20,11/26] riscv: Allocate user's vector context in the first-use trap [-next,v20,12/26] riscv: Add ptrace vector support [-next,v20,13/26] riscv: signal: check fp-reserved words unconditionally [-next,v20,14/26] riscv: signal: Add sigcontext save/restore for vector [-next,v20,15/26] riscv: signal: Report signal frame size to userspace via auxv [-next,v20,16/26] riscv: signal: validate altstack to reflect Vector [-next,v20,17/26] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v20,18/26] riscv: kvm: Add V extension to KVM ISA [-next,v20,19/26] riscv: KVM: Add vector lazy save/restore support [-next,v20,20/26] riscv: Add prctl controls for userspace vector management [-next,v20,21/26] riscv: Add sysctl to set the default vector rule for new processes [-next,v20,22/26] riscv: detect assembler support for .option arch [-next,v20,23/26] riscv: Enable Vector code to be built [-next,v20,24/26] riscv: Add documentation for Vector [-next,v20,25/26] selftests: Test RISC-V Vector prctl interface [-next,v20,26/26] selftests: add .gitignore file for RISC-V hwprobe

Message ID

20230518161949.11203-19-andy.chiu@sifive.com (mailing list archive)

State

New, archived

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        anup@brainfault.org, atishp@atishpatra.org,
        kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
        guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
        Andy Chiu <andy.chiu@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH -next v20 18/26] riscv: kvm: Add V extension to KVM ISA
Date: Thu, 18 May 2023 16:19:41 +0000
Message-Id: <20230518161949.11203-19-andy.chiu@sifive.com>
In-Reply-To: <20230518161949.11203-1-andy.chiu@sifive.com>
References: <20230518161949.11203-1-andy.chiu@sifive.com>
Precedence: bulk

Series

riscv: Add vector ISA support | expand

Commit Message

Andy Chiu May 18, 2023, 4:19 p.m. UTC

From: Vincent Chen <vincent.chen@sifive.com>

Add V extension to KVM isa extension list to enable supporting of V
extension on VCPUs.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index f92790c9481a..8feb57c4c2e8 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -121,6 +121,7 @@  enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZICBOZ,
 	KVM_RISCV_ISA_EXT_ZBB,
 	KVM_RISCV_ISA_EXT_SSAIA,
+	KVM_RISCV_ISA_EXT_V,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 8bd9f2a8a0b9..f3282ff371ca 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -57,6 +57,7 @@  static const unsigned long kvm_isa_ext_arr[] = {
 	[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
 	[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
 	[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
+	[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
 
 	KVM_ISA_EXT_ARR(SSAIA),
 	KVM_ISA_EXT_ARR(SSTC),

[-next,v20,18/26] riscv: kvm: Add V extension to KVM ISA

Commit Message

Patch