[-next,v20,05/26] riscv: Clear vector regfile on bootup

Message ID	20230518161949.11203-6-andy.chiu@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Vincent Chen <vincent.chen@sifive.com>, Guo Ren <guoren@kernel.org>, Masahiro Yamada <masahiroy@kernel.org>, Alexandre Ghiti <alex@ghiti.fr> Subject: [PATCH -next v20 05/26] riscv: Clear vector regfile on bootup Date: Thu, 18 May 2023 16:19:28 +0000 Message-Id: <20230518161949.11203-6-andy.chiu@sifive.com> In-Reply-To: <20230518161949.11203-1-andy.chiu@sifive.com> References: <20230518161949.11203-1-andy.chiu@sifive.com> Precedence: bulk
Series	riscv: Add vector ISA support \| expand [-next,v20,00/26] riscv: Add vector ISA support [-next,v20,01/26] riscv: Rename __switch_to_aux() -> fpu [-next,v20,02/26] riscv: Extending cpufeature.c to detect V-extension [-next,v20,03/26] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 [-next,v20,04/26] riscv: Add new csr defines related to vector extension [-next,v20,05/26] riscv: Clear vector regfile on bootup [-next,v20,06/26] riscv: Disable Vector Instructions for kernel itself [-next,v20,07/26] riscv: Introduce Vector enable/disable helpers [-next,v20,08/26] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v20,09/26] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v20,10/26] riscv: Add task switch support for vector [-next,v20,11/26] riscv: Allocate user's vector context in the first-use trap [-next,v20,12/26] riscv: Add ptrace vector support [-next,v20,13/26] riscv: signal: check fp-reserved words unconditionally [-next,v20,14/26] riscv: signal: Add sigcontext save/restore for vector [-next,v20,15/26] riscv: signal: Report signal frame size to userspace via auxv [-next,v20,16/26] riscv: signal: validate altstack to reflect Vector [-next,v20,17/26] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v20,18/26] riscv: kvm: Add V extension to KVM ISA [-next,v20,19/26] riscv: KVM: Add vector lazy save/restore support [-next,v20,20/26] riscv: Add prctl controls for userspace vector management [-next,v20,21/26] riscv: Add sysctl to set the default vector rule for new processes [-next,v20,22/26] riscv: detect assembler support for .option arch [-next,v20,23/26] riscv: Enable Vector code to be built [-next,v20,24/26] riscv: Add documentation for Vector [-next,v20,25/26] selftests: Test RISC-V Vector prctl interface [-next,v20,26/26] selftests: add .gitignore file for RISC-V hwprobe

Message ID

20230518161949.11203-6-andy.chiu@sifive.com (mailing list archive)

State

New, archived

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        anup@brainfault.org, atishp@atishpatra.org,
        kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
        guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Heiko Stuebner <heiko.stuebner@vrull.eu>,
        Vincent Chen <vincent.chen@sifive.com>,
        Guo Ren <guoren@kernel.org>,
        Masahiro Yamada <masahiroy@kernel.org>,
        Alexandre Ghiti <alex@ghiti.fr>
Subject: [PATCH -next v20 05/26] riscv: Clear vector regfile on bootup
Date: Thu, 18 May 2023 16:19:28 +0000
Message-Id: <20230518161949.11203-6-andy.chiu@sifive.com>
In-Reply-To: <20230518161949.11203-1-andy.chiu@sifive.com>
References: <20230518161949.11203-1-andy.chiu@sifive.com>
Precedence: bulk

Series

riscv: Add vector ISA support | expand

Commit Message

Andy Chiu May 18, 2023, 4:19 p.m. UTC

From: Greentime Hu <greentime.hu@sifive.com>

clear vector registers on boot if kernel supports V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4bf6c449d78b..3fd6a4bd9c3e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -392,7 +392,7 @@  ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	beqz	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done_fpu
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
@@ -430,8 +430,31 @@  ENTRY(reset_regs)
 	fmv.s.x	f31, zero
 	csrw	fcsr, 0
 	/* note that the caller must clear SR_FS */
+.Lreset_regs_done_fpu:
 #endif /* CONFIG_FPU */
-.Lreset_regs_done:
+
+#ifdef CONFIG_RISCV_ISA_V
+	csrr	t0, CSR_MISA
+	li	t1, COMPAT_HWCAP_ISA_V
+	and	t0, t0, t1
+	beqz	t0, .Lreset_regs_done_vector
+
+	/*
+	 * Clear vector registers and reset vcsr
+	 * VLMAX has a defined value, VLEN is a constant,
+	 * and this form of vsetvli is defined to set vl to VLMAX.
+	 */
+	li	t1, SR_VS
+	csrs	CSR_STATUS, t1
+	csrs	CSR_VCSR, x0
+	vsetvli t1, x0, e8, m8, ta, ma
+	vmv.v.i v0, 0
+	vmv.v.i v8, 0
+	vmv.v.i v16, 0
+	vmv.v.i v24, 0
+	/* note that the caller must clear SR_VS */
+.Lreset_regs_done_vector:
+#endif /* CONFIG_RISCV_ISA_V */
 	ret
 END(reset_regs)
 #endif /* CONFIG_RISCV_M_MODE */

[-next,v20,05/26] riscv: Clear vector regfile on bootup

Commit Message

Patch