[v13,09/30] LoongArch: KVM: Implement vcpu get, vcpu set registers

Message ID	20230609090832.2131037-10-zhaotianrui@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Tianrui Zhao <zhaotianrui@loongson.cn> To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini <pbonzini@redhat.com>, Huacai Chen <chenhuacai@kernel.org>, WANG Xuerui <kernel@xen0n.name>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, loongarch@lists.linux.dev, Jens Axboe <axboe@kernel.dk>, Mark Brown <broonie@kernel.org>, Alex Deucher <alexander.deucher@amd.com>, Oliver Upton <oliver.upton@linux.dev>, maobibo@loongson.cn, Xi Ruoyao <xry111@xry111.site>, zhaotianrui@loongson.cn, tangyouling@loongson.cn Subject: [PATCH v13 09/30] LoongArch: KVM: Implement vcpu get, vcpu set registers Date: Fri, 9 Jun 2023 17:08:11 +0800 Message-Id: <20230609090832.2131037-10-zhaotianrui@loongson.cn> In-Reply-To: <20230609090832.2131037-1-zhaotianrui@loongson.cn> References: <20230609090832.2131037-1-zhaotianrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add KVM LoongArch support \| expand [v13,00/30] Add KVM LoongArch support [v13,01/30] LoongArch: KVM: Add kvm related header files [v13,04/30] LoongArch: KVM: Implement VM related functions [v13,05/30] LoongArch: KVM: Add vcpu related header files [v13,06/30] LoongArch: KVM: Implement vcpu create and destroy interface [v13,07/30] LoongArch: KVM: Implement vcpu run interface [v13,08/30] LoongArch: KVM: Implement vcpu handle exit interface [v13,09/30] LoongArch: KVM: Implement vcpu get, vcpu set registers [v13,10/30] LoongArch: KVM: Implement vcpu ENABLE_CAP ioctl interface [v13,11/30] LoongArch: KVM: Implement fpu related operations for vcpu [v13,12/30] LoongArch: KVM: Implement vcpu interrupt operations [v13,13/30] LoongArch: KVM: Implement misc vcpu related interfaces [v13,14/30] LoongArch: KVM: Implement vcpu load and vcpu put operations [v13,17/30] LoongArch: KVM: Implement virtual machine tlb operations [v13,19/30] LoongArch: KVM: Implement kvm mmu operations [v13,20/30] LoongArch: KVM: Implement handle csr excption [v13,21/30] LoongArch: KVM: Implement handle iocsr exception [v13,22/30] LoongArch: KVM: Implement handle idle exception [v13,23/30] LoongArch: KVM: Implement handle gspr exception [v13,24/30] LoongArch: KVM: Implement handle mmio exception [v13,25/30] LoongArch: KVM: Implement handle fpu exception [v13,26/30] LoongArch: KVM: Implement kvm exception vector [v13,27/30] LoongArch: KVM: Implement vcpu world switch [v13,28/30] LoongArch: KVM: Enable kvm config and add the makefile [v13,29/30] LoongArch: KVM: Supplement kvm document about LoongArch-specific part [v13,30/30] LoongArch: KVM: Add maintainers for LoongArch KVM

diff --git a/arch/loongarch/kvm/csr_ops.S b/arch/loongarch/kvm/csr_ops.S new file mode 100644 index 000000000000..8a149af3241b --- /dev/null +++ b/arch/loongarch/kvm/csr_ops.S @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2023 Loongson Technology Corporation Limited + */ + +#include <asm/regdef.h> +#include <linux/linkage.h> + .text + .section .text + .cfi_sections .debug_frame +/* + * we have splited hw gcsr into three parts, so we can + * calculate the code offset by gcsrid and jump here to + * run the gcsrwr instruction. + */ +SYM_FUNC_START(set_hw_gcsr) + addi.d t0, a0, 0 + addi.w t1, zero, 96 + bltu t1, t0, 1f + la.pcrel t0, 10f + alsl.d t0, a0, t0, 3 + jr t0 +1: + addi.w t1, a0, -128 + addi.w t2, zero, 15 + bltu t2, t1, 2f + la.pcrel t0, 11f + alsl.d t0, t1, t0, 3 + jr t0 +2: + addi.w t1, a0, -384 + addi.w t2, zero, 3 + bltu t2, t1, 3f + la.pcrel t0, 12f + alsl.d t0, t1, t0, 3 + jr t0 +3: + addi.w a0, zero, -1 + jr ra +/* + * write guest csr + * 0x05000000 | (LOONGARCH_CSR_XXX << 10) | 1 << 5 | a1 + * range from 0x0(KVM_CSR_CRMD) to 0x60 (KVM_CSR_LLBCTL) + */ +10: + csrnum = 0 + .rept 0x61 + .word 0x05000020 | csrnum << 10 | 5 + jr ra + csrnum = csrnum + 1 + .endr +/* + * write guest csr + * 0x05000000 | (LOONGARCH_CSR_XXX << 10) | 1<<5 | a1 + * range from 0x80 (KVM_CSR_IMPCTL1) to 0x8f (KVM_CSR_TLBRPRMD) + */ +11: + csrnum = 0x80 + .rept 0x10 + .word 0x05000020 | csrnum << 10 | 5 + jr ra + csrnum = csrnum + 1 + .endr +/* + * write guest csr + * 0x05000000 | (LOONGARCH_CSR_XXX << 10) | 1<<5 | a1 + * range from 0x180(KVM_CSR_DMWIN0) to 0x183(KVM_CSR_DMWIN3) + */ +12: + csrnum = 0x180 + .rept 0x4 + .word 0x05000020 | csrnum << 10 | 5 + jr ra + csrnum = csrnum + 1 + .endr +SYM_FUNC_END(set_hw_gcsr) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index a45e9d9efe5b..b0cce413762d 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -12,6 +12,212 @@ #define CREATE_TRACE_POINTS #include "trace.h" +int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *v) +{ + unsigned long val; + struct loongarch_csrs *csr = vcpu->arch.csr; + + if (get_gcsr_flag(id) & INVALID_GCSR) + return -EINVAL; + + if (id == LOONGARCH_CSR_ESTAT) { + /* interrupt status IP0 -- IP7 from GINTC */ + val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff; + *v = kvm_read_sw_gcsr(csr, id) | (val << 2); + return 0; + } + + /* + * get software csr state if csrid is valid, since software + * csr state is consistent with hardware + */ + *v = kvm_read_sw_gcsr(csr, id); + + return 0; +} + +int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) +{ + struct loongarch_csrs *csr = vcpu->arch.csr; + int ret = 0, gintc; + + if (get_gcsr_flag(id) & INVALID_GCSR) + return -EINVAL; + + if (id == LOONGARCH_CSR_ESTAT) { + /* estat IP0~IP7 inject through guestexcept */ + gintc = (val >> 2) & 0xff; + write_csr_gintc(gintc); + kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); + + gintc = val & ~(0xffUL << 2); + write_gcsr_estat(gintc); + kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc); + + return ret; + } + + if (get_gcsr_flag(id) & HW_GCSR) { + set_hw_gcsr(id, val); + /* write sw gcsr to keep consistent with hardware */ + kvm_write_sw_gcsr(csr, id, val); + } else + kvm_write_sw_gcsr(csr, id, val); + + return ret; +} + +static int _kvm_get_one_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, s64 *v) +{ + int reg_idx, ret = 0; + + if ((reg->id & KVM_REG_LOONGARCH_MASK) == KVM_REG_LOONGARCH_CSR) { + reg_idx = KVM_GET_IOC_CSRIDX(reg->id); + ret = _kvm_getcsr(vcpu, reg_idx, v); + } else if (reg->id == KVM_REG_LOONGARCH_COUNTER) + *v = drdtime() + vcpu->kvm->arch.time_offset; + else + ret = -EINVAL; + + return ret; +} + +static int _kvm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + int ret = -EINVAL; + s64 v; + + if ((reg->id & KVM_REG_SIZE_MASK) != KVM_REG_SIZE_U64) + return ret; + + if (_kvm_get_one_reg(vcpu, reg, &v)) + return ret; + + return put_user(v, (u64 __user *)(long)reg->addr); +} + +static int _kvm_set_one_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + s64 v) +{ + int ret = 0; + unsigned long flags; + u64 val; + int reg_idx; + + val = v; + if ((reg->id & KVM_REG_LOONGARCH_MASK) == KVM_REG_LOONGARCH_CSR) { + reg_idx = KVM_GET_IOC_CSRIDX(reg->id); + ret = _kvm_setcsr(vcpu, reg_idx, val); + } else if (reg->id == KVM_REG_LOONGARCH_COUNTER) { + local_irq_save(flags); + /* + * gftoffset is relative with board, not vcpu + * only set for the first time for smp system + */ + if (vcpu->vcpu_id == 0) + vcpu->kvm->arch.time_offset = (signed long)(v - drdtime()); + write_csr_gcntc((ulong)vcpu->kvm->arch.time_offset); + local_irq_restore(flags); + } else if (reg->id == KVM_REG_LOONGARCH_VCPU_RESET) { + kvm_reset_timer(vcpu); + memset(&vcpu->arch.irq_pending, 0, sizeof(vcpu->arch.irq_pending)); + memset(&vcpu->arch.irq_clear, 0, sizeof(vcpu->arch.irq_clear)); + } else + ret = -EINVAL; + + return ret; +} + +static int _kvm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) +{ + s64 v; + int ret = -EINVAL; + + if ((reg->id & KVM_REG_SIZE_MASK) != KVM_REG_SIZE_U64) + return ret; + + if (get_user(v, (u64 __user *)(long)reg->addr)) + return ret; + + return _kvm_set_one_reg(vcpu, reg, v); +} + +int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, + struct kvm_sregs *sregs) +{ + return -ENOIOCTLCMD; +} + +int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, + struct kvm_sregs *sregs) +{ + return -ENOIOCTLCMD; +} + +int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + int i; + + vcpu_load(vcpu); + + for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) + regs->gpr[i] = vcpu->arch.gprs[i]; + + regs->pc = vcpu->arch.pc; + + vcpu_put(vcpu); + return 0; +} + +int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) +{ + int i; + + vcpu_load(vcpu); + + for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) + vcpu->arch.gprs[i] = regs->gpr[i]; + vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ + vcpu->arch.pc = regs->pc; + + vcpu_put(vcpu); + return 0; +} + +long kvm_arch_vcpu_ioctl(struct file *filp, + unsigned int ioctl, unsigned long arg) +{ + struct kvm_vcpu *vcpu = filp->private_data; + void __user *argp = (void __user *)arg; + long r; + + vcpu_load(vcpu); + + switch (ioctl) { + case KVM_SET_ONE_REG: + case KVM_GET_ONE_REG: { + struct kvm_one_reg reg; + + r = -EFAULT; + if (copy_from_user(&reg, argp, sizeof(reg))) + break; + if (ioctl == KVM_SET_ONE_REG) + r = _kvm_set_reg(vcpu, &reg); + else + r = _kvm_get_reg(vcpu, &reg); + break; + } + default: + r = -ENOIOCTLCMD; + break; + } + + vcpu_put(vcpu); + return r; +} + int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) { return 0;

[v13,09/30] LoongArch: KVM: Implement vcpu get, vcpu set registers

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