Message ID | 20230725152430.3351564-7-apatel@ventanamicro.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | RISC-V AIA irqchip and Svnapot support | expand |
diff --git a/Makefile b/Makefile index acd5ffd..d84dc8e 100644 --- a/Makefile +++ b/Makefile @@ -223,9 +223,11 @@ ifeq ($(ARCH),riscv) OBJS += riscv/aia.o ifeq ($(RISCV_XLEN),32) CFLAGS += -mabi=ilp32d -march=rv32gc + GUEST_INIT_FLAGS += -mabi=ilp32d -march=rv32gc endif ifeq ($(RISCV_XLEN),64) CFLAGS += -mabi=lp64d -march=rv64gc + GUEST_INIT_FLAGS += -mabi=lp64d -march=rv64gc endif ARCH_WANT_LIBFDT := y
For RISC-V multilib toolchains, we must specify -mabi and -march options when linking guest/init. Fixes: 2e99678314c2 ("riscv: Initial skeletal support") Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- Makefile | 2 ++ 1 file changed, 2 insertions(+)