@@ -509,7 +509,7 @@ struct kvm_pmc {
#define KVM_INTEL_PMC_MAX_GENERIC 8
#define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
#define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
-#define KVM_PMC_MAX_FIXED 3
+#define KVM_PMC_MAX_FIXED 4
#define MSR_ARCH_PERFMON_FIXED_CTR_MAX (MSR_ARCH_PERFMON_FIXED_CTR0 + KVM_PMC_MAX_FIXED - 1)
#define KVM_AMD_PMC_MAX_GENERIC 6
struct kvm_pmu {
@@ -45,6 +45,14 @@ enum intel_pmu_architectural_events {
* core crystal clock or the bus clock (yeah, "architectural").
*/
PSEUDO_ARCH_REFERENCE_CYCLES = NR_REAL_INTEL_ARCH_EVENTS,
+ /*
+ * Pseudo-architectural event used to implement IA32_FIXED_CTR3, a.k.a.
+ * topDown slots. The topdown slots event counts the total number of
+ * available slots for an unhalted logical processor. The topdwon slots
+ * event with PERF_METRICS MSR together provides support for topdown
+ * micro-architecture analysis method.
+ */
+ PSEUDO_ARCH_TOPDOWN_SLOTS,
NR_INTEL_ARCH_EVENTS,
};
@@ -61,6 +69,7 @@ static struct {
[INTEL_ARCH_BRANCHES_MISPREDICTED] = { 0xc5, 0x00 },
[INTEL_ARCH_TOPDOWN_SLOTS] = { 0xa4, 0x01 },
[PSEUDO_ARCH_REFERENCE_CYCLES] = { 0x00, 0x03 },
+ [PSEUDO_ARCH_TOPDOWN_SLOTS] = { 0x00, 0x04 },
};
/* mapping between fixed pmc index and intel_arch_events array */
@@ -68,6 +77,7 @@ static int fixed_pmc_events[] = {
[0] = INTEL_ARCH_INSTRUCTIONS_RETIRED,
[1] = INTEL_ARCH_CPU_CYCLES,
[2] = PSEUDO_ARCH_REFERENCE_CYCLES,
+ [3] = PSEUDO_ARCH_TOPDOWN_SLOTS,
};
static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
@@ -1459,7 +1459,7 @@ static const u32 msrs_to_save_base[] = {
static const u32 msrs_to_save_pmu[] = {
MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
- MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
+ MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3,
MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
@@ -7180,7 +7180,7 @@ static void kvm_init_msr_lists(void)
{
unsigned i;
- BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
+ BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 4,
"Please update the fixed PMCs in msrs_to_save_pmu[]");
num_msrs_to_save = 0;
The TopDown slots event can be enabled on gp counter or fixed counter 3 and it does not differ from other fixed counters in terms of the use of count and sampling modes (except for the hardware logic for event accumulation). According to commit 6017608936c1 ("perf/x86/intel: Add Icelake support"), KVM or any perf in-kernel user needs to reprogram fixed counter 3 via the kernel-defined TopDown slots event for real fixed counter 3 on the host. Co-developed-by: Like Xu <likexu@tencent.com> Signed-off-by: Like Xu <likexu@tencent.com> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 10 ++++++++++ arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 13 insertions(+), 3 deletions(-)