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Mon, 4 Sep 2023 09:57:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343B.mail.protection.outlook.com (10.167.18.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Mon, 4 Sep 2023 09:57:14 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 4 Sep 2023 04:57:10 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 11/13] KVM: SVM: Add support for IBS virtualization for SEV-ES guests Date: Mon, 4 Sep 2023 09:53:45 +0000 Message-ID: <20230904095347.14994-12-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|DM4PR12MB5182:EE_ X-MS-Office365-Filtering-Correlation-Id: 87fea6c2-763e-4e6d-ef1e-08dbad2d50f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:57:14.5795 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87fea6c2-763e-4e6d-ef1e-08dbad2d50f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5182 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since the IBS state is swap type C, the hypervisor is responsible for saving its own IBS state before VMRUN and restoring it after VMEXIT. It is also responsible for disabling IBS before VMRUN and re-enabling it after VMEXIT. For a SEV-ES guest with IBS virtualization enabled, a VMEXIT_INVALID will happen if IBS is found to be enabled on VMRUN [1]. The IBS virtualization feature for SEV-ES guests is not enabled in this patch. Later patches enable IBS virtualization for SEV-ES guests. [1]: https://bugzilla.kernel.org/attachment.cgi?id=304653 AMD64 Architecture Programmer’s Manual, Vol 2, Section 15.38 Instruction-Based Sampling Virtualization. Signed-off-by: Manali Shukla --- arch/x86/include/asm/svm.h | 14 +++++++++++++- arch/x86/kvm/svm/sev.c | 7 +++++++ arch/x86/kvm/svm/svm.c | 11 +++++------ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 4096d2f68770..58b60842a3b7 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -469,6 +469,18 @@ struct sev_es_save_area { u8 fpreg_x87[80]; u8 fpreg_xmm[256]; u8 fpreg_ymm[256]; + u8 lbr_stack_from_to[256]; + u64 lbr_select; + u64 ibs_fetch_ctl; + u64 ibs_fetch_linear_addr; + u64 ibs_op_ctl; + u64 ibs_op_rip; + u64 ibs_op_data; + u64 ibs_op_data2; + u64 ibs_op_data3; + u64 ibs_dc_linear_addr; + u64 ibs_br_target; + u64 ibs_fetch_extd_ctl; } __packed; struct ghcb_save_area { @@ -527,7 +539,7 @@ struct ghcb { #define EXPECTED_VMCB_SAVE_AREA_SIZE 1992 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 -#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 +#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1992 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 #define EXPECTED_GHCB_SIZE PAGE_SIZE diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index d3aec1f2cad2..41706335cedd 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -59,6 +59,7 @@ module_param_named(sev_es, sev_es_enabled, bool, 0444); #define sev_es_enabled false #endif /* CONFIG_KVM_AMD_SEV */ +static bool sev_es_vibs_enabled; static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -2256,6 +2257,9 @@ void __init sev_hardware_setup(void) sev_enabled = sev_supported; sev_es_enabled = sev_es_supported; + + if (!sev_es_enabled || !cpu_feature_enabled(X86_FEATURE_SEV_ES_VIBS)) + sev_es_vibs_enabled = false; #endif } @@ -2993,6 +2997,9 @@ static void sev_es_init_vmcb(struct vcpu_svm *svm) if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_RDTSCP)) svm_clr_intercept(svm, INTERCEPT_RDTSCP); } + + if (sev_es_vibs_enabled && svm->ibs_enabled) + svm_ibs_msr_interception(svm, false); } void sev_init_vmcb(struct vcpu_svm *svm) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 6f566ed93f4c..0cfe23bb144a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4194,16 +4194,15 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_in guest_state_enter_irqoff(); amd_clear_divider(); + restore_mask = svm_save_swap_type_c(vcpu); - if (sev_es_guest(vcpu->kvm)) { + if (sev_es_guest(vcpu->kvm)) __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted); - } else { - restore_mask = svm_save_swap_type_c(vcpu); + else __svm_vcpu_run(svm, spec_ctrl_intercepted); - if (restore_mask) - svm_restore_swap_type_c(vcpu, restore_mask); - } + if (restore_mask) + svm_restore_swap_type_c(vcpu, restore_mask); guest_state_exit_irqoff(); }