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Mon, 4 Sep 2023 09:57:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343D.mail.protection.outlook.com (10.167.18.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Mon, 4 Sep 2023 09:57:24 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 4 Sep 2023 04:57:14 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 12/13] KVM: SVM: Enable IBS virtualization on non SEV-ES and SEV-ES guests Date: Mon, 4 Sep 2023 09:53:46 +0000 Message-ID: <20230904095347.14994-13-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|CY8PR12MB7241:EE_ X-MS-Office365-Filtering-Correlation-Id: e1a08aed-07f1-447c-03a1-08dbad2d56f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:57:24.6503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1a08aed-07f1-447c-03a1-08dbad2d56f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7241 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To enable IBS virtualization capability on non SEV-ES guests, bit 2 at offset 0xb8 in VMCB is set to 1 for non SEV-ES guests. To enable IBS virtualization capability on SEV-ES guests, bit 12 in SEV_FEATURES in VMSA is set to 1 for SEV-ES guests. Signed-off-by: Manali Shukla --- arch/x86/include/asm/svm.h | 4 ++++ arch/x86/kvm/svm/sev.c | 5 ++++- arch/x86/kvm/svm/svm.c | 26 +++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 58b60842a3b7..a31bf803b993 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -215,6 +215,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define LBR_CTL_ENABLE_MASK BIT_ULL(0) #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) +#define VIRTUAL_IBS_ENABLE_MASK BIT_ULL(2) + #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0) #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1) @@ -259,6 +261,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL +#define SVM_SEV_ES_FEAT_VIBS BIT(12) + #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 41706335cedd..e0ef3a2323d6 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -59,7 +59,7 @@ module_param_named(sev_es, sev_es_enabled, bool, 0444); #define sev_es_enabled false #endif /* CONFIG_KVM_AMD_SEV */ -static bool sev_es_vibs_enabled; +static bool sev_es_vibs_enabled = true; static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -607,6 +607,9 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->xss = svm->vcpu.arch.ia32_xss; save->dr6 = svm->vcpu.arch.dr6; + if (svm->ibs_enabled && sev_es_vibs_enabled) + save->sev_features |= SVM_SEV_ES_FEAT_VIBS; + pr_debug("Virtual Machine Save Area (VMSA):\n"); print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 0cfe23bb144a..b85120f0d3ac 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -234,7 +234,7 @@ static int lbrv = true; module_param(lbrv, int, 0444); /* enable/disable IBS virtualization */ -static int vibs; +static int vibs = true; module_param(vibs, int, 0444); static int tsc_scaling = true; @@ -1245,10 +1245,13 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) /* * If hardware supports VIBS then no need to intercept IBS MSRS * when VIBS is enabled in guest. + * + * Enable VIBS by setting bit 2 at offset 0xb8 in VMCB. */ if (vibs) { if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_IBS)) { svm_ibs_msr_interception(svm, false); + svm->vmcb->control.virt_ext |= VIRTUAL_IBS_ENABLE_MASK; svm->ibs_enabled = true; /* @@ -5166,6 +5169,24 @@ static __init void svm_adjust_mmio_mask(void) kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK); } +static void svm_ibs_set_cpu_caps(void) +{ + kvm_cpu_cap_set(X86_FEATURE_IBS); + kvm_cpu_cap_set(X86_FEATURE_EXTLVT); + kvm_cpu_cap_set(X86_FEATURE_EXTAPIC); + kvm_cpu_cap_set(X86_FEATURE_IBS_AVAIL); + kvm_cpu_cap_set(X86_FEATURE_IBS_FETCHSAM); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPSAM); + kvm_cpu_cap_set(X86_FEATURE_IBS_RDWROPCNT); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPCNT); + kvm_cpu_cap_set(X86_FEATURE_IBS_BRNTRGT); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPCNTEXT); + kvm_cpu_cap_set(X86_FEATURE_IBS_RIPINVALIDCHK); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPBRNFUSE); + kvm_cpu_cap_set(X86_FEATURE_IBS_FETCHCTLEXTD); + kvm_cpu_cap_set(X86_FEATURE_IBS_ZEN4_EXT); +} + static __init void svm_set_cpu_caps(void) { kvm_set_cpu_caps(); @@ -5208,6 +5229,9 @@ static __init void svm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK); } + if (vibs) + svm_ibs_set_cpu_caps(); + /* CPUID 0x80000008 */ if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) || boot_cpu_has(X86_FEATURE_AMD_SSBD))