| Message ID | 20230922085701.3164-4-yongxuan.wang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
On Fri, Sep 22, 2023 at 08:56:49AM +0000, Yong-Xuan Wang wrote: > We extend the KVM ISA extension ONE_REG interface to allow VMM > tools to detect and enable Svadu extension for Guest/VM. > > Also set the HADE bit in henvcfg CSR if Svadu extension is > available for Guest/VM. > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu.c | 3 +++ > arch/riscv/kvm/vcpu_onereg.c | 1 + > 3 files changed, 5 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index 992c5e407104..3c7a6c762d0f 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -131,6 +131,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZICSR, > KVM_RISCV_ISA_EXT_ZIFENCEI, > KVM_RISCV_ISA_EXT_ZIHPM, > + KVM_RISCV_ISA_EXT_SVADU, This register will show up as "new" in kselftests test[1]. We should add another patch to this series to update the test to handle/test it. [1] tools/testing/selftests/kvm/riscv/get-reg-list.c > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 82229db1ce73..91b92a1f4e33 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -487,6 +487,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) > if (riscv_isa_extension_available(isa, ZICBOZ)) > henvcfg |= ENVCFG_CBZE; > > + if (riscv_isa_extension_available(isa, SVADU)) > + henvcfg |= ENVCFG_HADE; > + > csr_write(CSR_HENVCFG, henvcfg); > #ifdef CONFIG_32BIT > csr_write(CSR_HENVCFGH, henvcfg >> 32); > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index 1b7e9fa265cb..211915dad677 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > /* Multi letter extensions (alphabetically sorted) */ > KVM_ISA_EXT_ARR(SSAIA), > KVM_ISA_EXT_ARR(SSTC), > + KVM_ISA_EXT_ARR(SVADU), > KVM_ISA_EXT_ARR(SVINVAL), > KVM_ISA_EXT_ARR(SVNAPOT), > KVM_ISA_EXT_ARR(SVPBMT), > -- > 2.17.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 992c5e407104..3c7a6c762d0f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -131,6 +131,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZICSR, KVM_RISCV_ISA_EXT_ZIFENCEI, KVM_RISCV_ISA_EXT_ZIHPM, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 82229db1ce73..91b92a1f4e33 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -487,6 +487,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (riscv_isa_extension_available(isa, ZICBOZ)) henvcfg |= ENVCFG_CBZE; + if (riscv_isa_extension_available(isa, SVADU)) + henvcfg |= ENVCFG_HADE; + csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 1b7e9fa265cb..211915dad677 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = { /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT),
We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svadu extension for Guest/VM. Also set the HADE bit in henvcfg CSR if Svadu extension is available for Guest/VM. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_onereg.c | 1 + 3 files changed, 5 insertions(+)