| Message ID | 20231016132819.1002933-6-michael.roth@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add AMD Secure Nested Paging (SEV-SNP) Hypervisor Support | expand |
On Mon, Oct 16, 2023 at 08:27:34AM -0500, Michael Roth wrote: > From: Kim Phillips <kim.phillips@amd.com> > > Without SEV-SNP, Automatic IBRS protects only the kernel. But when > SEV-SNP is enabled, the Automatic IBRS protection umbrella widens to all > host-side code, including userspace. This protection comes at a cost: > reduced userspace indirect branch performance. > > To avoid this performance loss, don't use Automatic IBRS on SEV-SNP > hosts. Fall back to retpolines instead. > > Signed-off-by: Kim Phillips <kim.phillips@amd.com> > [mdr: squash in changes from review discussion] > Signed-off-by: Michael Roth <michael.roth@amd.com> > --- > arch/x86/kernel/cpu/common.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
On 10/16/23 06:27, Michael Roth wrote: > Without SEV-SNP, Automatic IBRS protects only the kernel. But when > SEV-SNP is enabled, the Automatic IBRS protection umbrella widens to all > host-side code, including userspace. This protection comes at a cost: > reduced userspace indirect branch performance. > > To avoid this performance loss, don't use Automatic IBRS on SEV-SNP > hosts. Fall back to retpolines instead. Thanks for the updated changelog: Acked-by: Dave Hansen <dave.hansen@intel.com> BTW, have you given your hardware folks a hard time about this? It seems _kinda_ silly to be using retpolines when the hardware has a perfectly good IBRS implementation for the kernel. Just please make sure there's a good underlying reason for this behavior and as opposed to being some kind of inadvertent side effect. I assume Auto-IBRS and SEV-SNP are going to be with us for a long time, so it would be nice to have a long term solution here.
On 10/16/23 15:27, Michael Roth wrote: > From: Kim Phillips <kim.phillips@amd.com> > > Without SEV-SNP, Automatic IBRS protects only the kernel. But when > SEV-SNP is enabled, the Automatic IBRS protection umbrella widens to all > host-side code, including userspace. This protection comes at a cost: > reduced userspace indirect branch performance. > > To avoid this performance loss, don't use Automatic IBRS on SEV-SNP > hosts. Fall back to retpolines instead. > > Signed-off-by: Kim Phillips <kim.phillips@amd.com> > [mdr: squash in changes from review discussion] > Signed-off-by: Michael Roth <michael.roth@amd.com> Queued, thanks. Paolo > --- > arch/x86/kernel/cpu/common.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > index 382d4e6b848d..11fae89b799e 100644 > --- a/arch/x86/kernel/cpu/common.c > +++ b/arch/x86/kernel/cpu/common.c > @@ -1357,8 +1357,13 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) > /* > * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature > * flag and protect from vendor-specific bugs via the whitelist. > + * > + * Don't use AutoIBRS when SNP is enabled because it degrades host > + * userspace indirect branch performance. > */ > - if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { > + if ((ia32_cap & ARCH_CAP_IBRS_ALL) || > + (cpu_has(c, X86_FEATURE_AUTOIBRS) && > + !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { > setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); > if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && > !(ia32_cap & ARCH_CAP_PBRSB_NO))
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 382d4e6b848d..11fae89b799e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1357,8 +1357,13 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) /* * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature * flag and protect from vendor-specific bugs via the whitelist. + * + * Don't use AutoIBRS when SNP is enabled because it degrades host + * userspace indirect branch performance. */ - if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { + if ((ia32_cap & ARCH_CAP_IBRS_ALL) || + (cpu_has(c, X86_FEATURE_AUTOIBRS) && + !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) { setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && !(ia32_cap & ARCH_CAP_PBRSB_NO))