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Sun, 29 Oct 2023 09:00:40 -0700 From: Yishai Hadas To: , , , CC: , , , , , , , , , , Subject: [PATCH V2 vfio 8/9] vfio/pci: Expose vfio_pci_iowrite/read##size() Date: Sun, 29 Oct 2023 17:59:51 +0200 Message-ID: <20231029155952.67686-9-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231029155952.67686-1-yishaih@nvidia.com> References: <20231029155952.67686-1-yishaih@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|CY5PR12MB6106:EE_ X-MS-Office365-Filtering-Correlation-Id: 79ff22c6-02c7-47bd-6589-08dbd89837ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: K9e8+PRsS+k4e24+sfxL5wAvw21aN7abug4HXH6Mmmy3aVOcbl6OL9tuHQxJxnySmqcd6I0QrKydSzvWNLcnUxboeBSd81DzMfOBOoz3oNmCzZCW7zSLAXSLmGCGc2bHoNA6VH91BV86D5WhyNk/+JIUFkMOUxbXhwf0Sz+HICJQB6TLVt8gifoj75un8J3ikZal12x3z34vR7Llu0Q0OB/XIKzGirVJ6RvFTHWNLmCTVKs1O+Cfl81NG6bO/R0/Y/AuEQ+FksRTagVzDLFfJhGnJfipqEO+rDhg4b6Wr9RICldwIRitK4IlfQ65K8eCeC5RUHf5cqbB2HA0fYOgBVVV5lRs7ysfgIzZ2REmmZglvA98iUJaB1/ru7V2JavI1JH9vjkHvrXhatbeYkk4fKLXHK1HvixxjSskmeIcMRHuVYEydYvNwbeZ4ZyqhMoUk1UlU1vTGDR7nL5NjaEl5UV6ywsLRnuWCzVE4nxTTNvVSFki+kDyCdLsYkHS76D6s4GBFD8TAcMnFKCV1+92ogJcEyUauXaja1oQDLqBZmElLJ7+zu3YAT1O2A5oXQhfOSf5RZnG5gVWaWp+otH9JWYcJgr01hghM+IMEQbA4DWOibWkh/EnKRuyvbZQ+7KkcObJKT3SNNRuzsUj4A08Mvdrvn/dVamlvITfayiim7tznTUGenbo/KXe6YqiR8JuyxWBa2xDquwjMmRD6ohv8+L73IqMjZhGMSo7O8kqj+KDolSRsF2OeFdlm+2gFu67Biu1sjfaABL4lLe210B2fA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(346002)(136003)(39860400002)(230922051799003)(64100799003)(82310400011)(451199024)(1800799009)(186009)(40470700004)(36840700001)(46966006)(2906002)(5660300002)(41300700001)(6636002)(40480700001)(40460700003)(356005)(26005)(4326008)(82740400003)(7636003)(83380400001)(8676002)(70586007)(8936002)(107886003)(110136005)(54906003)(1076003)(6666004)(36860700001)(36756003)(2616005)(478600001)(7696005)(316002)(70206006)(426003)(86362001)(336012)(47076005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 16:00:48.6649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79ff22c6-02c7-47bd-6589-08dbd89837ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6106 Expose vfio_pci_iowrite/read##size() to let it be used by drivers. This functionality is needed to enable direct access to some physical BAR of the device with the proper locks/checks in place. The next patches from this series will use this functionality on a data path flow when a direct access to the BAR is needed. Signed-off-by: Yishai Hadas --- drivers/vfio/pci/vfio_pci_rdwr.c | 10 ++++++---- include/linux/vfio_pci_core.h | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 6f08b3ecbb89..817ec9a89123 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -38,7 +38,7 @@ #define vfio_iowrite8 iowrite8 #define VFIO_IOWRITE(size) \ -static int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev, \ +int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev, \ bool test_mem, u##size val, void __iomem *io) \ { \ if (test_mem) { \ @@ -55,7 +55,8 @@ static int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev, \ up_read(&vdev->memory_lock); \ \ return 0; \ -} +} \ +EXPORT_SYMBOL_GPL(vfio_pci_iowrite##size); VFIO_IOWRITE(8) VFIO_IOWRITE(16) @@ -65,7 +66,7 @@ VFIO_IOWRITE(64) #endif #define VFIO_IOREAD(size) \ -static int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev, \ +int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev, \ bool test_mem, u##size *val, void __iomem *io) \ { \ if (test_mem) { \ @@ -82,7 +83,8 @@ static int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev, \ up_read(&vdev->memory_lock); \ \ return 0; \ -} +} \ +EXPORT_SYMBOL_GPL(vfio_pci_ioread##size); VFIO_IOREAD(8) VFIO_IOREAD(16) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 67ac58e20e1d..22c915317788 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -131,4 +131,23 @@ int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar); pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, pci_channel_state_t state); +#define VFIO_IOWRITE_DECLATION(size) \ +int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev, \ + bool test_mem, u##size val, void __iomem *io); + +VFIO_IOWRITE_DECLATION(8) +VFIO_IOWRITE_DECLATION(16) +VFIO_IOWRITE_DECLATION(32) +#ifdef iowrite64 +VFIO_IOWRITE_DECLATION(64) +#endif + +#define VFIO_IOREAD_DECLATION(size) \ +int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev, \ + bool test_mem, u##size *val, void __iomem *io); + +VFIO_IOREAD_DECLATION(8) +VFIO_IOREAD_DECLATION(16) +VFIO_IOREAD_DECLATION(32) + #endif /* VFIO_PCI_CORE_H */