From patchwork Wed Nov 15 07:14:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13456300 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02135DDAA for ; Wed, 15 Nov 2023 07:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TwkdOFah" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2785D1 for ; Tue, 14 Nov 2023 23:18:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700032684; x=1731568684; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zo7sfFltxczgMHIRkUAysmMSa6bA704Q/pIzo3LmMUM=; b=TwkdOFahw4ivstxg832FLLaeOT3qUPGY9H9XGgUCqBXsPbBXzC9GyCvd 9GA5Idm2JT0IxmurGniC/S9mzYhHxGlH3kadkbIZTs9g8hT07Q3+VXgrR xrZi1mxnsX0hMM9dV4l8kuoWrsaAQ6M7+6L9ZybZTmmrf3eaijs6X7Y+g fhLEYeskeZ9NjJd740f7hBHUAnhKSUCE6mx4z70VdXMG2l1PXiKbMwkeH Sg2vlzR0Mj9sDZpoqxIkd4UojusxVnifs6uoNPOokcbnx5zcJOGxi01Sj uNrdEWp7JfqIkUYw7mqMqv+SUv+sMb1RLEFsveOsk4KqfUuFifF4o/S43 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="390622663" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="390622663" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2023 23:18:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="714798207" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="714798207" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orsmga003.jf.intel.com with ESMTP; 14 Nov 2023 23:17:57 -0800 From: Xiaoyao Li To: Paolo Bonzini , David Hildenbrand , Igor Mammedov , "Michael S . Tsirkin" , Marcel Apfelbaum , Richard Henderson , Peter Xu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com, Michael Roth , Sean Christopherson , Claudio Fontana , Gerd Hoffmann , Isaku Yamahata , Chenyi Qiang Subject: [PATCH v3 23/70] i386/tdx: Integrate tdx_caps->attrs_fixed0/1 to tdx_cpuid_lookup Date: Wed, 15 Nov 2023 02:14:32 -0500 Message-Id: <20231115071519.2864957-24-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231115071519.2864957-1-xiaoyao.li@intel.com> References: <20231115071519.2864957-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some bits in TD attributes have corresponding CPUID feature bits. Reflect the fixed0/1 restriction on TD attributes to their corresponding CPUID bits in tdx_cpuid_lookup[] as well. Signed-off-by: Xiaoyao Li --- target/i386/cpu-internal.h | 9 +++++++++ target/i386/cpu.c | 9 --------- target/i386/cpu.h | 2 ++ target/i386/kvm/tdx.c | 21 +++++++++++++++++++++ 4 files changed, 32 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9baac5c0b450..e980f6e3147f 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -20,6 +20,15 @@ #ifndef I386_CPU_INTERNAL_H #define I386_CPU_INTERNAL_H +typedef struct FeatureMask { + FeatureWord index; + uint64_t mask; +} FeatureMask; + +typedef struct FeatureDep { + FeatureMask from, to; +} FeatureDep; + typedef enum FeatureWordType { CPUID_FEATURE_WORD, MSR_FEATURE_WORD, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 128b01054ff3..e66b7a8b7b8d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1442,15 +1442,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, }; -typedef struct FeatureMask { - FeatureWord index; - uint64_t mask; -} FeatureMask; - -typedef struct FeatureDep { - FeatureMask from, to; -} FeatureDep; - static FeatureDep feature_dependencies[] = { { .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d0b7ba5d113e..23265d890074 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -876,6 +876,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_0_ECX_MAWAU (31U << 17) /* Read Processor ID */ #define CPUID_7_0_ECX_RDPID (1U << 22) +/* KeyLocker */ +#define CPUID_7_0_ECX_KeyLocker (1U << 23) /* Bus Lock Debug Exception */ #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) /* Cache Line Demote Instruction */ diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index be7771bd97d7..1f5d8117d1a9 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -32,6 +32,13 @@ (1U << KVM_FEATURE_PV_SCHED_YIELD) | \ (1U << KVM_FEATURE_MSI_EXT_DEST_ID)) +#define TDX_ATTRIBUTES_MAX_BITS 64 + +static FeatureMask tdx_attrs_ctrl_fields[TDX_ATTRIBUTES_MAX_BITS] = { + [30] = { .index = FEAT_7_0_ECX, .mask = CPUID_7_0_ECX_PKS }, + [31] = { .index = FEAT_7_0_ECX, .mask = CPUID_7_0_ECX_KeyLocker}, +}; + typedef struct KvmTdxCpuidLookup { uint32_t tdx_fixed0; uint32_t tdx_fixed1; @@ -380,6 +387,8 @@ static void update_tdx_cpuid_lookup_by_tdx_caps(void) FeatureWordInfo *fi; uint32_t config; FeatureWord w; + FeatureMask *fm; + int i; /* * Patch tdx_fixed0/1 by tdx_caps that what TDX module reports as @@ -401,6 +410,18 @@ static void update_tdx_cpuid_lookup_by_tdx_caps(void) entry->tdx_fixed1 &= ~config; } + for (i = 0; i < ARRAY_SIZE(tdx_attrs_ctrl_fields); i++) { + fm = &tdx_attrs_ctrl_fields[i]; + + if (tdx_caps->attrs_fixed0 & (1ULL << i)) { + tdx_cpuid_lookup[fm->index].tdx_fixed0 |= fm->mask; + } + + if (tdx_caps->attrs_fixed1 & (1ULL << i)) { + tdx_cpuid_lookup[fm->index].tdx_fixed1 |= fm->mask; + } + } + /* * Because KVM gets XFAM settings via CPUID leaves 0xD, map * tdx_caps->xfam_fixed{0, 1} into tdx_cpuid_lookup[].tdx_fixed{0, 1}.