From patchwork Wed Nov 15 07:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13456367 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45A833D9F for ; Wed, 15 Nov 2023 07:23:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TfeB2Pff" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03D66F7 for ; Tue, 14 Nov 2023 23:23:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700033003; x=1731569003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dg2iwoS+KZjVsX1SZQ4VkazcO/ckeGCsKvKoPEilg9M=; b=TfeB2PffStPA/7crch0XrBWDNOro0lfi66AT3gpzmymPuAX/hLTUfUHd yZglpSu2uScFuuAsyrJaCkXG0RfB9vKzEEFXf/Vw7BIGfFKTmNvLZyrUo xY5cRYgmYl5ANUMu3D294hcZgLCqeVmz+ff6qSDqvyqef4PJFiP4DR7pB LjzWAf9ZR/2WRfMnuhmz+F2hDyrJ0aGBk0135psnifdo1C0Tj4XWAf/SZ tkpcL5eRz9YA8OU08b2t6oDOdRMfR78R9nARMNbyVb4GKOV5uuTvo+Xlq ETwwOsOzbF6ZM1HekYA1OWoKSsTifIHA/zo93gXWm6e9B8LiT0KpDTVWq Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="390623596" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="390623596" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2023 23:23:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="714800382" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="714800382" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orsmga003.jf.intel.com with ESMTP; 14 Nov 2023 23:23:17 -0800 From: Xiaoyao Li To: Paolo Bonzini , David Hildenbrand , Igor Mammedov , "Michael S . Tsirkin" , Marcel Apfelbaum , Richard Henderson , Peter Xu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com, Michael Roth , Sean Christopherson , Claudio Fontana , Gerd Hoffmann , Isaku Yamahata , Chenyi Qiang Subject: [PATCH v3 61/70] i386/tdx: Disable PIC for TDX VMs Date: Wed, 15 Nov 2023 02:15:10 -0500 Message-Id: <20231115071519.2864957-62-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231115071519.2864957-1-xiaoyao.li@intel.com> References: <20231115071519.2864957-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Legacy PIC (8259) cannot be supported for TDX VMs since TDX module doesn't allow directly interrupt injection. Using posted interrupts for the PIC is not a viable option as the guest BIOS/kernel will not do EOI for PIC IRQs, i.e. will leave the vIRR bit set. Hence disable PIC for TDX VMs and error out if user wants PIC. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- target/i386/kvm/tdx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 45b587ee07c2..208fe3572839 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -699,6 +699,13 @@ int tdx_kvm_init(MachineState *ms, Error **errp) return -EINVAL; } + if (x86ms->pic == ON_OFF_AUTO_AUTO) { + x86ms->pic = ON_OFF_AUTO_OFF; + } else if (x86ms->pic == ON_OFF_AUTO_ON) { + error_setg(errp, "TDX VM doesn't support PIC"); + return -EINVAL; + } + if (!tdx_caps) { r = get_tdx_capabilities(errp); if (r) {