From patchwork Tue Nov 28 14:53:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471312 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="BU3gv/si" Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 126C4199A for ; Tue, 28 Nov 2023 06:55:11 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1cfd78f8a12so17207805ad.2 for ; Tue, 28 Nov 2023 06:55:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183311; x=1701788111; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=airu/v47wgDNqhAY8kBHQ9N6G4glvU45jZqVuvQoU4M=; b=BU3gv/sik7JGzsYntxTVPetFJLPNqWByjFpBs7k/3HkOMFPlL50YQw5bXzkgkMs53c O4xC/3PNpTJaChDbOnDw/pQ/X6BhCVjD2dyvd11iorQi1LobCsRYcLqEcCSjK+n8Dutw C+OU0DN+Mkx6LC0N+tWvHmFSLKeoV4IC38oetWbGx7RrLE7/MoV6j4OCGNYZ4ZX7Hgxv tAuCIvhkIppqMhJ/Oir/bq58QuW3IJrC+Efq52iYfuJEVLrcHVHtVWONZGub/qYuBYG4 OIms+iC9YkWnv9ElVB1iXgxx4oAnTaMpgF7cl06YxNxegK8nozCKo+4pJmvCYSVq9DMc oSbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183311; x=1701788111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=airu/v47wgDNqhAY8kBHQ9N6G4glvU45jZqVuvQoU4M=; b=U2+kxZoLPowo801wSocpiWpwZm0/FM7GO0swBqH7dHck3dtbfPo9M8iPft0y7sCSwD viogSlhcK18jfp7Do+VYRwMObWsdUgjRLvthpweXkhsLqmX1eC5+WJJUnpjTaRy7OCKZ 9Sih/ohGjgAcGP50aQk78PKqLlCEb5owN5LhvgcDR6NuepaB5tRUcIoOOygPO4ZAJ0BL ivG0t22X9NCTgLq8KhHFtzGZ5szVNQzn/oVgmq3stSeGAYX3VcicT+bUkQTkonEeUjBL bzrw1Qy960tNyevNWgi/+IpPKWtXmiO1LKBOPdfXBEnrevG1p+DVm/qQbaCb7Ya8g2vR 1iYw== X-Gm-Message-State: AOJu0YzAQfEeEaAUxIwUkf4FjNfkL5v8Kqx6E4HZlEpXcbkcQVruhA7s nHPcWFRQIEJAePfX9EMA0QzhVQ== X-Google-Smtp-Source: AGHT+IH4ZKbRH0sAoue+ms9u+mc6iPKravgS7x++zKnn9LjeTNQidu/8LuA2QuuAYh4M2kbbBqG+gQ== X-Received: by 2002:a17:902:e88f:b0:1cf:cf40:3cef with SMTP id w15-20020a170902e88f00b001cfcf403cefmr6689569plg.64.1701183311308; Tue, 28 Nov 2023 06:55:11 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id u11-20020a170902e80b00b001bf11cf2e21sm10281552plg.210.2023.11.28.06.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:55:10 -0800 (PST) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Shuah Khan Cc: Anup Patel , Andrew Jones , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 12/15] RISC-V: KVM: Allow Zvfh[min] extensions for Guest/VM Date: Tue, 28 Nov 2023 20:23:54 +0530 Message-Id: <20231128145357.413321-13-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145357.413321-1-apatel@ventanamicro.com> References: <20231128145357.413321-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zvfh[min] extensions for Guest/VM. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu_onereg.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 0ed5b0f8a230..32c7ff23ecce 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -163,6 +163,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFH, KVM_RISCV_ISA_EXT_ZFHMIN, KVM_RISCV_ISA_EXT_ZIHINTNTL, + KVM_RISCV_ISA_EXT_ZVFH, + KVM_RISCV_ISA_EXT_ZVFHMIN, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index ba0a44b6b757..6b2d81c8cfe7 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -67,6 +67,8 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZKT), KVM_ISA_EXT_ARR(ZVBB), KVM_ISA_EXT_ARR(ZVBC), + KVM_ISA_EXT_ARR(ZVFH), + KVM_ISA_EXT_ARR(ZVFHMIN), KVM_ISA_EXT_ARR(ZVKB), KVM_ISA_EXT_ARR(ZVKG), KVM_ISA_EXT_ARR(ZVKNED), @@ -139,6 +141,8 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZKT: case KVM_RISCV_ISA_EXT_ZVBB: case KVM_RISCV_ISA_EXT_ZVBC: + case KVM_RISCV_ISA_EXT_ZVFH: + case KVM_RISCV_ISA_EXT_ZVFHMIN: case KVM_RISCV_ISA_EXT_ZVKB: case KVM_RISCV_ISA_EXT_ZVKG: case KVM_RISCV_ISA_EXT_ZVKNED: