@@ -226,7 +226,6 @@ asm_mmu_disable:
ldr r0, [r0]
ldr r1, =__phys_end
ldr r1, [r1]
- sub r1, r1, r0
dcache_by_line_op dccimvac, sy, r0, r1, r2, r3
mov pc, lr
@@ -264,7 +264,6 @@ asm_mmu_disable:
ldr x0, [x0, :lo12:__phys_offset]
adrp x1, __phys_end
ldr x1, [x1, :lo12:__phys_end]
- sub x1, x1, x0
dcache_by_line_op civac, sy, x0, x1, x2, x3
ret
@@ -25,17 +25,16 @@
/*
* Macro to perform a data cache maintenance for the interval
- * [addr, addr + size).
+ * [addr, end).
*
* op: operation to execute
* domain domain used in the dsb instruction
* addr: starting virtual address of the region
- * size: size of the region
- * Corrupts: addr, size, tmp1, tmp2
+ * end: the end of the region (non-inclusive)
+ * Corrupts: addr, tmp1, tmp2
*/
- .macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2
+ .macro dcache_by_line_op op, domain, addr, end, tmp1, tmp2
dcache_line_size \tmp1, \tmp2
- add \size, \addr, \size
sub \tmp2, \tmp1, #1
bic \addr, \addr, \tmp2
9998:
@@ -45,7 +44,7 @@
.err
.endif
add \addr, \addr, \tmp1
- cmp \addr, \size
+ cmp \addr, \end
blo 9998b
dsb \domain
.endm
@@ -28,25 +28,24 @@
/*
* Macro to perform a data cache maintenance for the interval
- * [addr, addr + size). Use the raw value for the dcache line size because
+ * [addr, end). Use the raw value for the dcache line size because
* kvm-unit-tests has no concept of scheduling.
*
* op: operation passed to dc instruction
* domain: domain used in dsb instruction
* addr: starting virtual address of the region
- * size: size of the region
- * Corrupts: addr, size, tmp1, tmp2
+ * end: the end of the region (non-inclusive)
+ * Corrupts: addr, tmp1, tmp2
*/
- .macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2
+ .macro dcache_by_line_op op, domain, addr, end, tmp1, tmp2
raw_dcache_line_size \tmp1, \tmp2
- add \size, \addr, \size
sub \tmp2, \tmp1, #1
bic \addr, \addr, \tmp2
9998:
dc \op, \addr
add \addr, \addr, \tmp1
- cmp \addr, \size
+ cmp \addr, \end
b.lo 9998b
dsb \domain
.endm