From patchwork Tue Dec 5 17:45:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13480516 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="A+qQp/ju" Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64F45122 for ; Tue, 5 Dec 2023 09:45:30 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1d0c94397c0so6193075ad.2 for ; Tue, 05 Dec 2023 09:45:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701798330; x=1702403130; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xDmx5prnNC5GcsIkGu5R3qOSAEa8hCYanFPPTHn90qw=; b=A+qQp/jusDzJjFMMnN5+QTKEgABCTB+AYukhP4UK0fBkRFnqwg/XWQ4WZgHH7r7N10 ifLnmqc5kB3/JcrvxOfbsZs4V8ASZpyrPJDeSbv1N+dmGd48OUlKTsYNZL+IeiUaumUF M+v4a+AB8nqkA9xdhJ6alBzmGI0Pw6FojG8FzvEehY9OnwHb417IRm9C7+nt1TKx89CG O/C0ITvitesZOKoJXjqnHc04Aye6Mcd/8Q43JgvaLJ3NZZeAN0BEmXuyM3CUD92rgGst wV0uPP7CfGpvnzLj0h+M/xfWb/dXruoeoesxRbYIsAe4/I3BYnamsosrLknaEDdX4P1q 5TNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701798330; x=1702403130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xDmx5prnNC5GcsIkGu5R3qOSAEa8hCYanFPPTHn90qw=; b=Ie4NjY4K7dHC1f8iojpzSunIgxJwAwPf2+JnbHliJjNByFFN82x7GSD6wypaLPsesG bvOyB0WXGtvEqE2OhH2MSwii/u/GoFRAJ4RuAq5F2Fw9u0MGS74NvdSuT8RNDdHjXrkk VElSIZsS99f7Q1Mfy8YFi5XXsvCc4IHGNWznlGFrBFlkdeSH4wxaYpsRPqV22CY1aBRk a9E9wiwb4zq3wjQ5P88/OcGS9mDOXp1d6hqZlNiUNVAZiQwEDgw8FuBU8sBi7slv/syy 1hUw/o0bx68o/aZevts0Q4oSmc5j4SHbo+aGmsegi7/v25gkqauIYa3bfGIpejwsMAFo sVvQ== X-Gm-Message-State: AOJu0Yxf1OUqg6VPXtdBp9hQt+YBQKdkE/LZO6ciaXHMKKwbLfrHA8D+ H62n8PkZPKj/aSWurUYXYe1xOg== X-Google-Smtp-Source: AGHT+IF1UZLtbstXiLGAqb3dZPBrPK0Kg5I3E3SNIV6kA8JjlJ2QhfhiGUU2Udk2N9DtQEvBJyDFVw== X-Received: by 2002:a17:902:748c:b0:1d0:b033:4a98 with SMTP id h12-20020a170902748c00b001d0b0334a98mr2747236pll.17.1701798329723; Tue, 05 Dec 2023 09:45:29 -0800 (PST) Received: from grind.. ([152.234.124.8]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001c74df14e6fsm10465705pll.284.2023.12.05.09.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 09:45:29 -0800 (PST) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Date: Tue, 5 Dec 2023 14:45:08 -0300 Message-ID: <20231205174509.2238870-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231205174509.2238870-1-dbarboza@ventanamicro.com> References: <20231205174509.2238870-1-dbarboza@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise it is not possible to retrieve any vector reg since we're returning EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()). Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_vector.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index 530e49c588d6..d92d1348045c 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -116,6 +116,9 @@ static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): *reg_addr = &cntx->vector.vcsr; break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): + *reg_addr = &cntx->vector.vlenb; + break; case KVM_REG_RISCV_VECTOR_CSR_REG(datap): default: return -ENOENT; @@ -174,6 +177,18 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, if (!riscv_isa_extension_available(isa, v)) return -ENOENT; + if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) { + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long reg_val; + + if (copy_from_user(®_val, uaddr, reg_size)) + return -EFAULT; + if (reg_val != cntx->vector.vlenb) + return -EINVAL; + + return 0; + } + rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_addr); if (rc) return rc;