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Thu, 21 Dec 2023 07:40:32 -0800 From: To: , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v5 3/4] kvm: arm64: set io memory s2 pte as normalnc for vfio pci devices Date: Thu, 21 Dec 2023 21:10:01 +0530 Message-ID: <20231221154002.32622-4-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231221154002.32622-1-ankita@nvidia.com> References: <20231221154002.32622-1-ankita@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|DM6PR12MB4530:EE_ X-MS-Office365-Filtering-Correlation-Id: bf7f2a21-cc1b-4078-15e9-08dc023b3b16 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +W+szar1QmHDe0BIL+42ckDW1lABQ+6vw+OcE4G+kpGqaNty5zLq5uKN/z5ocGEjlZ3ghM+vTl2efBg4uR/8CYh4WbpNdtiDhZNGAJIA1yHIlw1DZYY9hbOkXhBa+ti6ET75Rt01dCsm6V8ec28letVoSVxTostapKer2PtCzNmLLlr1LerJZPv6WPzle1vOH89YIicwSNE6f47R33wEZQmcDXg7z15DYbLst7crlyg26HPsVOicepk4GZgZZH0E2Sg8TCqjs3K6iI4oOe2W7/zDiWkvcgQh44xcqHGessOGc5b/E4oeX9oed74d+0XiWmmVdS6Rl6JeMKR4w3wLG/l4W+C7ufSpeIZwNLhC37Yu2f/BE6VEYLCf32kMOBOfVMKBuiPSx0whZyO2cfbhPFlNvXxYHUW9/luzasMsoeEyr7z7yKmsxA4TVoWCtndlSGjrEGrWhXB+3/uk++uyDwEjhY73s7JYsBX3NF7roEjERIKDKip6lNZsf1lv++IDA4abxTTkFK65khOwqOF9VQZkSolg2+uvLMIb77MwVVwFess48QIqYdrIMRK47YbJ2+zn78d7X4bAtYTLoXWNKfJn9ZJcACmXStw76i3WTgRxW30zqqkjpxOBvd8/Tv5/hzhk8KTBaK/59+1iKNwt+6OUjO3LP5l9yQ3+TJ4aFuiJB3ueVGXoQOwkWozv88lOl7x5fNY6iBENBr+H5xUb9t+MpU5m8DyOU+YnxqbeP33sEDVDe8eL0LOZTMAa+wLg7k/g5i561zONzh8Q0KkJ94VGYhjNdEpPeW0vvXTzrkH1ArWuJOh/FMs7/Z/xHFNV X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(346002)(376002)(39860400002)(230922051799003)(451199024)(1800799012)(64100799003)(186009)(82310400011)(46966006)(36840700001)(40470700004)(40460700003)(26005)(2616005)(1076003)(336012)(83380400001)(426003)(6666004)(7696005)(47076005)(36860700001)(5660300002)(7416002)(2906002)(41300700001)(2876002)(478600001)(8676002)(4326008)(70586007)(8936002)(70206006)(110136005)(316002)(54906003)(356005)(7636003)(36756003)(86362001)(82740400003)(921008)(40480700001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2023 15:40:59.6303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf7f2a21-cc1b-4078-15e9-08dc023b3b16 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4530 From: Ankit Agrawal To provide VM with the ability to get device IO memory with NormalNC property, map device MMIO in KVM for ARM64 at stage2 as NormalNC. Having NormalNC S2 default puts guests in control (based on [1], "Combining stage 1 and stage 2 memory type attributes") of device MMIO regions memory mappings. The rules are summarized below: ([(S1) - stage1], [(S2) - stage 2]) S1 | S2 | Result NORMAL-WB | NORMAL-NC | NORMAL-NC NORMAL-WT | NORMAL-NC | NORMAL-NC NORMAL-NC | NORMAL-NC | NORMAL-NC DEVICE | NORMAL-NC | DEVICE Still this cannot be generalized to non PCI devices such as GICv2. There is insufficient information and uncertainity in the behavior of non PCI driver. A driver must indicate support using the new flag VM_VFIO_ALLOW_WC. Adapt KVM to make use of the flag VM_VFIO_ALLOW_WC as indicator to activate the S2 setting to NormalNc. [1] section D8.5.5 of DDI0487J_a_a-profile_architecture_reference_manual.pdf Signed-off-by: Ankit Agrawal Suggested-by: Catalin Marinas Acked-by: Jason Gunthorpe Tested-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index d87c8fcc4c24..7e01fff78e23 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1379,7 +1379,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, int ret = 0; bool write_fault, writable, force_pte = false; bool exec_fault, mte_allowed; - bool device = false; + bool device = false, vfio_allow_wc = false; unsigned long mmu_seq; struct kvm *kvm = vcpu->kvm; struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache; @@ -1471,6 +1471,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, gfn = fault_ipa >> PAGE_SHIFT; mte_allowed = kvm_vma_mte_allowed(vma); + vfio_allow_wc = (vma->vm_flags & VM_VFIO_ALLOW_WC); + /* Don't use the VMA after the unlock -- it may have vanished */ vma = NULL; @@ -1557,10 +1559,18 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, if (exec_fault) prot |= KVM_PGTABLE_PROT_X; - if (device) - prot |= KVM_PGTABLE_PROT_DEVICE; - else if (cpus_have_final_cap(ARM64_HAS_CACHE_DIC)) + if (device) { + /* + * To provide VM with the ability to get device IO memory + * with NormalNC property, map device MMIO as NormalNC in S2. + */ + if (vfio_allow_wc) + prot |= KVM_PGTABLE_PROT_NORMAL_NC; + else + prot |= KVM_PGTABLE_PROT_DEVICE; + } else if (cpus_have_final_cap(ARM64_HAS_CACHE_DIC)) { prot |= KVM_PGTABLE_PROT_X; + } /* * Under the premise of getting a FSC_PERM fault, we just need to relax