| Message ID | 20240112060042.19925-2-binbin.wu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for LAM in QEMU | expand |
On Fri, Jan 12, 2024 at 02:00:41PM +0800, Binbin Wu wrote: > Date: Fri, 12 Jan 2024 14:00:41 +0800 > From: Binbin Wu <binbin.wu@linux.intel.com> > Subject: [PATCH v4 1/2] target/i386: add support for LAM in CPUID > enumeration > X-Mailer: git-send-email 2.25.1 > > From: Robert Hoo <robert.hu@linux.intel.com> > > Linear Address Masking (LAM) is a new Intel CPU feature, which allows > software to use of the untranslated address bits for metadata. > > The bit definition: > CPUID.(EAX=7,ECX=1):EAX[26] > > Add CPUID definition for LAM. > > Note LAM feature is not supported for TCG of target-i386, LAM CPIUD bit > will not be added to TCG_7_1_EAX_FEATURES. > > More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)" > https://cdrdv2.intel.com/v1/dl/getContent/671368 > > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> > Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com> > Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com> > Tested-by: Xuelian Guo <xuelian.guo@intel.com> > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 2524881ce2..fc862dfeb1 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -967,7 +967,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > "fsrc", NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, "amx-fp16", NULL, "avx-ifma", > - NULL, NULL, NULL, NULL, > + NULL, NULL, "lam", NULL, > NULL, NULL, NULL, NULL, > }, > .cpuid = { > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 7f0786e8b9..18ea755644 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -925,6 +925,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, > #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) > /* Support for VPMADD52[H,L]UQ */ > #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) > +/* Linear Address Masking */ > +#define CPUID_7_1_EAX_LAM (1U << 26) > > /* Support for VPDPB[SU,UU,SS]D[,S] */ > #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) > -- > 2.25.1 > >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2524881ce2..fc862dfeb1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -967,7 +967,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "amx-fp16", NULL, "avx-ifma", - NULL, NULL, NULL, NULL, + NULL, NULL, "lam", NULL, NULL, NULL, NULL, NULL, }, .cpuid = { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..18ea755644 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -925,6 +925,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) /* Support for VPMADD52[H,L]UQ */ #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) +/* Linear Address Masking */ +#define CPUID_7_1_EAX_LAM (1U << 26) /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)