From patchwork Thu Jan 25 03:22:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13529878 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 612F9134DE for ; Thu, 25 Jan 2024 03:28:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706153321; cv=none; b=E9l8E/ZRSgU2WwfqNFFdlHkIyWsJJDZEhOWrzbhT3jUKCR+vPsjKK62Z/D7CPgvRAEotSyEstiR8qzOvvxE8sVEnuQHn3pgEG7EpPjzS1QWQn0d2hog6Qb1sFtlBP+U9ahvnRqEf+RxINBPsplzBY0wQPz+4d6BUIHpP1NMkXUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706153321; c=relaxed/simple; bh=FdNtZ3nORqbzp8x//sbHp9TjmlwalDB/lonLa69Au0Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FGyzoQ34sg8ia+z615PN8pysJueh3R9kDCpmN/GsgwsmJQEEnE+PCJTTgAPWhNlsfbptUUpUqgIWfPlCy50r6etfE8WwCX56WAuJpfZ1aq4z51sV98mdENkbJ9U/pmRVbT39QjuqHTsHaUxLt/hv1wlO3Rb7uGMT5He2Vokcdd8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MVJvDdIK; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MVJvDdIK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706153320; x=1737689320; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FdNtZ3nORqbzp8x//sbHp9TjmlwalDB/lonLa69Au0Y=; b=MVJvDdIKWIM1AZbuYd8xDlr5L9hrlX8mFwzwdjbRmMyOlRnY+Hfrt9SZ TCRsePEpFN6qHOpHSJLpgxa8gLOnZkFVd8nmsmtwgLZmnnh51RUsHVeYp oOINWk/gBTE4JGa6jdnXsjoal1SlE3TNslNLk+tDwq7wsUHxhfMFuBEU/ ROVDtKtEXdpSWNGM400UKpXc8iZR9eo72GA5I+s80kgnt9GChZx3y2SXu hqyzPrvijOYdLtjVzJfOjD6cBofPzdDLEL8u8Xn9Kx3rsdfCT8Mm54XYR PIR5rcv7/vBMOhVdn1Ws4oFDIq/fyx4k+jSAekPJjYBKQOjqNxjtPy362 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="9428886" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="9428886" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2024 19:26:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="2085685" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa005.jf.intel.com with ESMTP; 24 Jan 2024 19:26:01 -0800 From: Xiaoyao Li To: Paolo Bonzini , David Hildenbrand , Igor Mammedov , "Michael S . Tsirkin" , Marcel Apfelbaum , Richard Henderson , Peter Xu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cornelia Huck , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com, Michael Roth , Sean Christopherson , Claudio Fontana , Gerd Hoffmann , Isaku Yamahata , Chenyi Qiang Subject: [PATCH v4 27/66] i386/tdx: Wire CPU features up with attributes of TD guest Date: Wed, 24 Jan 2024 22:22:49 -0500 Message-Id: <20240125032328.2522472-28-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125032328.2522472-1-xiaoyao.li@intel.com> References: <20240125032328.2522472-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For QEMU VMs, PKS is configured via CPUID_7_0_ECX_PKS and PMU is configured by x86cpu->enable_pmu. Reuse the existing configuration interface for TDX VMs. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- target/i386/kvm/tdx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 91cd116fb153..1cb38b5d6221 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -33,6 +33,8 @@ (1U << KVM_FEATURE_MSI_EXT_DEST_ID)) #define TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE BIT_ULL(28) +#define TDX_TD_ATTRIBUTES_PKS BIT_ULL(30) +#define TDX_TD_ATTRIBUTES_PERFMON BIT_ULL(63) #define TDX_ATTRIBUTES_MAX_BITS 64 @@ -476,6 +478,15 @@ int tdx_kvm_init(MachineState *ms, Error **errp) return 0; } +static void setup_td_guest_attributes(X86CPU *x86cpu) +{ + CPUX86State *env = &x86cpu->env; + + tdx_guest->attributes |= (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS) ? + TDX_TD_ATTRIBUTES_PKS : 0; + tdx_guest->attributes |= x86cpu->enable_pmu ? TDX_TD_ATTRIBUTES_PERFMON : 0; +} + int tdx_pre_create_vcpu(CPUState *cpu, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -498,6 +509,8 @@ int tdx_pre_create_vcpu(CPUState *cpu, Error **errp) return r; } + setup_td_guest_attributes(x86cpu); + init_vm->cpuid.nent = kvm_x86_arch_cpuid(env, init_vm->cpuid.entries, 0); init_vm->attributes = tdx_guest->attributes;