diff mbox series

[RFC,14/41] KVM: x86/pmu: Allow RDPMC pass through

Message ID	20240126085444.324918-15-xiong.y.zhang@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23BA910A0F; Fri, 26 Jan 2024 08:56:50 +0000 (UTC) From: Xiong Zhang <xiong.y.zhang@linux.intel.com> To: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com Cc: kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, xiong.y.zhang@linux.intel.com, Xiong Zhang <xiong.y.zhang@intel.com> Subject: [RFC PATCH 14/41] KVM: x86/pmu: Allow RDPMC pass through Date: Fri, 26 Jan 2024 16:54:17 +0800 Message-Id: <20240126085444.324918-15-xiong.y.zhang@linux.intel.com> In-Reply-To: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	KVM: x86/pmu: Introduce passthrough vPM \| expand [RFC,00/41] KVM: x86/pmu: Introduce passthrough vPM [RFC,01/41] perf: x86/intel: Support PERF_PMU_CAP_VPMU_PASSTHROUGH [RFC,02/41] perf: Support guest enter/exit interfaces [RFC,03/41] perf: Set exclude_guest onto nmi_watchdog [RFC,04/41] perf: core/x86: Add support to register a new vector for PMI handling [RFC,05/41] KVM: x86/pmu: Register PMI handler for passthrough PMU [RFC,06/41] perf: x86: Add function to switch PMI handler [RFC,07/41] perf/x86: Add interface to reflect virtual LVTPC_MASK bit onto HW [RFC,08/41] KVM: x86/pmu: Add get virtual LVTPC_MASK bit function [RFC,09/41] perf: core/x86: Forbid PMI handler when guest own PMU [RFC,10/41] perf: core/x86: Plumb passthrough PMU capability from x86_pmu to x86_pmu_cap [RFC,11/41] KVM: x86/pmu: Introduce enable_passthrough_pmu module parameter and propage to KVM inst… [RFC,12/41] KVM: x86/pmu: Plumb through passthrough PMU to vcpu for Intel CPUs [RFC,13/41] KVM: x86/pmu: Add a helper to check if passthrough PMU is enabled [RFC,14/41] KVM: x86/pmu: Allow RDPMC pass through [RFC,15/41] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL [RFC,16/41] KVM: x86/pmu: Create a function prototype to disable MSR interception [RFC,17/41] KVM: x86/pmu: Implement pmu function for Intel CPU to disable MSR interception [RFC,18/41] KVM: x86/pmu: Intercept full-width GP counter MSRs by checking with perf capabilities [RFC,19/41] KVM: x86/pmu: Whitelist PMU MSRs for passthrough PMU [RFC,20/41] KVM: x86/pmu: Introduce PMU operation prototypes for save/restore PMU context [RFC,21/41] KVM: x86/pmu: Introduce function prototype for Intel CPU to save/restore PMU context [RFC,22/41] x86: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET for passthrough PMU [RFC,23/41] KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU [RFC,24/41] KVM: x86/pmu: Zero out unexposed Counters/Selectors to avoid information leakage [RFC,25/41] KVM: x86/pmu: Introduce macro PMU_CAP_PERF_METRICS [RFC,26/41] KVM: x86/pmu: Add host_perf_cap field in kvm_caps to record host PMU capability [RFC,27/41] KVM: x86/pmu: Clear PERF_METRICS MSR for guest [RFC,28/41] KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary [RFC,29/41] KVM: x86/pmu: Exclude existing vLBR logic from the passthrough PMU [RFC,30/41] KVM: x86/pmu: Switch PMI handler at KVM context switch boundary [RFC,31/41] KVM: x86/pmu: Call perf_guest_enter() at PMU context switch [RFC,32/41] KVM: x86/pmu: Add support for PMU context switch at VM-exit/enter [RFC,33/41] KVM: x86/pmu: Make check_pmu_event_filter() an exported function [RFC,34/41] KVM: x86/pmu: Intercept EVENT_SELECT MSR [RFC,35/41] KVM: x86/pmu: Allow writing to event selector for GP counters if event is allowed [RFC,36/41] KVM: x86/pmu: Intercept FIXED_CTR_CTRL MSR [RFC,37/41] KVM: x86/pmu: Allow writing to fixed counter selector if counter is exposed [RFC,38/41] KVM: x86/pmu: Introduce PMU helper to increment counter [RFC,39/41] KVM: x86/pmu: Implement emulated counter increment for passthrough PMU [RFC,40/41] KVM: x86/pmu: Separate passthrough PMU logic in set/get_msr() from non-passthrough vPMU [RFC,41/41] KVM: nVMX: Add nested virtualization support for passthrough PMU

Commit Message

Xiong Zhang Jan. 26, 2024, 8:54 a.m. UTC

From: Mingwei Zhang <mizhang@google.com>

Clear RDPMC_EXITING in vmcs cpu based execution control to allow rdpmc
instruction to proceed without VMEXIT. This gives performance to
passthrough PMU. Clear RDPMC in vmx_vcpu_after_set_cpuid() when guest
enables PMU and passthrough PMU is allowed.

The passthrough RDPMC allows guest to read several PMU MSRs including
unexposed counters like fixed counter 3 as well as IA32_PERF_METRICS.

To cope with this issue, these MSRs will be cleared in later commits when
context switching to VM guest.

Co-developed-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Mingwei Zhang <mizhang@google.com>
---
 arch/x86/kvm/vmx/vmx.c | 3 +++
 1 file changed, 3 insertions(+)

diff mbox series

Patch

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index e4610b80e519..33cb69ff0804 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7819,6 +7819,9 @@  static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
 		vmx->msr_ia32_feature_control_valid_bits &=
 			~FEAT_CTL_SGX_LC_ENABLED;
 
+	if (is_passthrough_pmu_enabled(&vmx->vcpu))
+		exec_controls_clearbit(vmx, CPU_BASED_RDPMC_EXITING);
+
 	/* Refresh #PF interception to account for MAXPHYADDR changes. */
 	vmx_update_exception_bitmap(vcpu);
 }