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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif_common.c | 5 +---- target/arm/cpu.c | 19 +++++-------------- target/arm/debug_helper.c | 8 ++------ target/arm/gdbstub.c | 6 ++---- target/arm/gdbstub64.c | 6 ++---- target/arm/helper.c | 9 +++------ target/arm/hvf/hvf.c | 12 ++++-------- target/arm/kvm.c | 3 +-- target/arm/ptw.c | 3 +-- target/arm/tcg/cpu32.c | 3 +-- 10 files changed, 22 insertions(+), 52 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c index ff1239f65d..bab3c3cdbd 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -15,8 +15,5 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; - - env->gicv3state = (void *)s; + cpu_env(cpu)->gicv3state = (void *)s; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 593695b424..3970223f33 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -51,8 +51,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (is_a64(env)) { env->pc = value; @@ -65,8 +64,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) static vaddr arm_cpu_get_pc(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (is_a64(env)) { return env->pc; @@ -994,19 +992,15 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - cpu_synchronize_state(cs); - return arm_cpu_data_is_big_endian(env); + return arm_cpu_data_is_big_endian(cpu_env(cs)); } #endif static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { - ARMCPU *ac = ARM_CPU(cpu); - CPUARMState *env = &ac->env; + CPUARMState *env = cpu_env(cpu); bool sctlr_b; if (is_a64(env)) { @@ -2428,10 +2422,7 @@ static Property arm_cpu_properties[] = { static const gchar *arm_gdb_arch_name(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_IWMMXT)) { return "iwmmxt"; } return "arm"; diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..7bd5467414 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -468,8 +468,7 @@ void arm_debug_excp_handler(CPUState *cs) * Called by core code when a watchpoint or breakpoint fires; * need to check which one and raise the appropriate exception. */ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); CPUWatchpoint *wp_hit = cs->watchpoint_hit; if (wp_hit) { @@ -757,9 +756,6 @@ void hw_breakpoint_update_all(ARMCPU *cpu) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - /* * In BE32 system mode, target memory is stored byteswapped (on a * little-endian host system), and by the time we reach here (via an @@ -767,7 +763,7 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) * to account for that, which means that watchpoints will not match. * Undo the adjustment here. */ - if (arm_sctlr_b(env)) { + if (arm_sctlr_b(cpu_env(cs))) { if (len == 1) { addr ^= 3; } else if (len == 2) { diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 28f546a5ff..dc6c29669c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -40,8 +40,7 @@ typedef struct RegisterSysregXmlParam { int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (n < 16) { /* Core integer register. */ @@ -61,8 +60,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); uint32_t tmp; tmp = ldl_p(mem_buf); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589..b9f29b0a60 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -24,8 +24,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (n < 31) { /* Core integer register. */ @@ -45,8 +44,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); uint64_t tmp; tmp = ldq_p(mem_buf); diff --git a/target/arm/helper.c b/target/arm/helper.c index e068d35383..a504ed0612 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10900,8 +10900,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. */ uint32_t addr, mask; - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); switch (cs->exception_index) { case EXCP_UDEF: @@ -10979,8 +10978,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); uint32_t addr; uint32_t mask; int new_mode; @@ -11479,8 +11477,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) #ifdef CONFIG_TCG static void tcg_handle_semihosting(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (is_a64(env)) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a537a5bc94..69211d0a60 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1004,8 +1004,7 @@ void hvf_kick_vcpu_thread(CPUState *cpu) static void hvf_raise_exception(CPUState *cpu, uint32_t excp, uint32_t syndrome) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); cpu->exception_index = excp; env->exception.target_el = 1; @@ -1483,8 +1482,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); trace_hvf_sysreg_write(reg, SYSREG_OP0(reg), @@ -2150,8 +2148,7 @@ static void hvf_put_gdbstub_debug_registers(CPUState *cpu) */ static void hvf_put_guest_debug_registers(CPUState *cpu) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); hv_return_t r = HV_SUCCESS; int i; @@ -2205,8 +2202,7 @@ static void hvf_arch_set_traps(void) void hvf_arch_update_guest_debug(CPUState *cpu) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); /* Check whether guest debugging is enabled */ cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8f52b211f9..9e97c847b3 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1957,8 +1957,7 @@ int kvm_arch_destroy_vcpu(CPUState *cs) /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { - ARMCPU *cpu = ARM_CPU(c); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(c); uint32_t esr; bool same_el; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5eb3577bcd..57a761ad68 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3528,8 +3528,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); ARMMMUIdx mmu_idx = arm_mmu_idx(env); ARMSecuritySpace ss = arm_security_space(env); S1Translate ptw = { diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..c11c5c85c4 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -102,8 +102,7 @@ void aa32_max_features(ARMCPU *cpu) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); bool ret = false; /*