From patchwork Wed Jan 31 10:13:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13539042 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E219769DED for ; Wed, 31 Jan 2024 10:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706695297; cv=none; b=Rb9YWjv3iSzPTSohexhJU+twGn86sVm+Kt8lK7diVAj09UpGDq/Cy13AOCzoChhoeV4L0ERKEUHc4nHb2KKgBV0S2zs4Yqa0CL58ZM+bQaAY5WWVE1FUawGzujTFMXy6J3yDwjvsmRuiDbyoZX3xfsBZlJwLi4q5vIs2R8N3cXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706695297; c=relaxed/simple; bh=zAYrvGnilidyHb6EeYs3757tIsjHx3c4fVsdy35rO84=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Qj7iXTMv7Nk/XmZCOJzUZHk+aLWogAddVyKPbSmoK+z2BMOLXsbkI0cNlAg897gFr1fyBytkUJu8GX5wJg0egXzojlfW9bjcCh1T9l7RH7MQDH24pa77KQL4flDPLNb4SPJ90S0LpsGNAnRSS5ozZrmxezs6NZI19pB4eoWEbyU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JUADsvqz; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JUADsvqz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706695296; x=1738231296; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zAYrvGnilidyHb6EeYs3757tIsjHx3c4fVsdy35rO84=; b=JUADsvqzUTSi+20XLbkYP1YlQqQWDAgRCFqgC52vcQAhJW2jD+jzZAK5 UOS4W5OOuB+DTcp2vAvWxHu06CBSqlkePgfA4FZv/xSPjz5qqNwdHpWLQ N4ObIQhEW1bVxCUXKeqwZQ0+zTBHb8Tmyb+Poi2MPHYATo7C0MBid2uEv aMzr1uBFkaM//iM9LLsHYuNocbU7jZ2HE0CMc9SjfWIDh7SS5aeH/vFWz Zx6ZtHAVUzZQ2NrhbcEzbnJ0OdXPHrrc29W9C810KuynSqS8OqVLJrAW/ hHehivOwS8cHTbNesPjRSnXSjTglL/Ls2QAvwNgt/ZCsXkAYMs4mzsss8 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="25032845" X-IronPort-AV: E=Sophos;i="6.05,231,1701158400"; d="scan'208";a="25032845" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2024 02:01:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,231,1701158400"; d="scan'208";a="4036122" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa003.fm.intel.com with ESMTP; 31 Jan 2024 02:01:30 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Babu Moger , Xiaoyao Li , Zhenyu Wang , Zhuocheng Ding , Yongwei Ma , Zhao Liu Subject: [PATCH v8 12/21] i386: Introduce module level cpu topology to CPUX86State Date: Wed, 31 Jan 2024 18:13:41 +0800 Message-Id: <20240131101350.109512-13-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101350.109512-1-zhao1.liu@linux.intel.com> References: <20240131101350.109512-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Intel CPUs implement module level on hybrid client products (e.g., ADL-N, MTL, etc) and E-core server products. A module contains a set of cores that share certain resources (in current products, the resource usually includes L2 cache, as well as module scoped features and MSRs). Module level support is the prerequisite for L2 cache topology on module level. With module level, we can implement the Guest's CPU topology and future cache topology to be consistent with the Host's on Intel hybrid client/E-core server platforms. Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu --- Changes since v7: * Mapped x86 module to smp module instead of cluster. * Re-wrote the commit message to explain the reason why we needs module level. * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v1: * The background of the introduction of the "cluster" parameter and its exact meaning were revised according to Yanan's explanation. (Yanan) --- hw/i386/x86.c | 5 +++++ target/i386/cpu.c | 1 + target/i386/cpu.h | 3 +++ 3 files changed, 9 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5a42e3757099..2ead995b0197 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -309,6 +309,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, init_topo_info(&topo_info, x86ms); + if (ms->smp.modules > 1) { + env->nr_modules = ms->smp.modules; + /* TODO: Expose module level in CPUID[0x1F]. */ + } + if (ms->smp.dies > 1) { env->nr_dies = ms->smp.dies; set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 81d2f0c42a0c..f1a0aa77a873 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7700,6 +7700,7 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) { CPUX86State *env = &cpu->env; + env->nr_modules = 1; env->nr_dies = 1; /* SMT, core and package levels are set by default. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8a7450f265a1..d0951a0fec27 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1892,6 +1892,9 @@ typedef struct CPUArchState { /* Number of dies within this CPU package. */ unsigned nr_dies; + /* Number of modules within this CPU package. */ + unsigned nr_modules; + /* Bitmap of available CPU topology levels for this CPU. */ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); } CPUX86State;