diff mbox series

[v8,09/16] x86/cpufeatures: Add synthetic Secure TSC bit

Message ID 20240215113128.275608-10-nikunj@amd.com (mailing list archive)
State New, archived
Headers show
Series Add Secure TSC support for SNP guests | expand

Commit Message

Nikunj A. Dadhania Feb. 15, 2024, 11:31 a.m. UTC 
Add support for the synthetic CPUID flag which indicates that the SNP
guest is running with secure tsc enabled (MSR_AMD64_SEV Bit 11 -
SecureTsc_Enabled) . This flag is there so that this capability in the
guests can be detected easily without reading MSRs every time accessors.

Suggested-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
Tested-by: Peter Gonda <pgonda@google.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Borislav Petkov April 22, 2024, 1:25 p.m. UTC | #1 
On Thu, Feb 15, 2024 at 05:01:21PM +0530, Nikunj A Dadhania wrote:
> Add support for the synthetic CPUID flag which indicates that the SNP
> guest is running with secure tsc enabled (MSR_AMD64_SEV Bit 11 -

"TSC"

> SecureTsc_Enabled) . This flag is there so that this capability in the
> guests can be detected easily without reading MSRs every time accessors.

Why?

What's wrong with cc_platform_has(CC_ATTR_GUEST_SECURE_TSC) or so?
Nikunj A. Dadhania April 23, 2024, 4:40 a.m. UTC | #2 
On 4/22/2024 6:55 PM, Borislav Petkov wrote:
> On Thu, Feb 15, 2024 at 05:01:21PM +0530, Nikunj A Dadhania wrote:
>> Add support for the synthetic CPUID flag which indicates that the SNP
>> guest is running with secure tsc enabled (MSR_AMD64_SEV Bit 11 -
> 
> "TSC"

Sure

> 
>> SecureTsc_Enabled) . This flag is there so that this capability in the
>> guests can be detected easily without reading MSRs every time accessors.
> 
> Why?
> 
> What's wrong with cc_platform_has(CC_ATTR_GUEST_SECURE_TSC) or so?
> 

That was the initial implementation, and there were review comments[1] to
use synthetic flag.

Regards
Nikunj

1. https://lore.kernel.org/lkml/20231106130041.gqoqszdxrmdomsxl@box.shutemov.name/
Borislav Petkov April 23, 2024, 1:29 p.m. UTC | #3 
On Tue, Apr 23, 2024 at 10:10:14AM +0530, Nikunj A. Dadhania wrote:
> 1. https://lore.kernel.org/lkml/20231106130041.gqoqszdxrmdomsxl@box.shutemov.name/

I have no clue what "We have better instrumentation around features."
means and am not convinced.
diff mbox series

Patch

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 0fa702673e73..24ac7fe97806 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -236,6 +236,7 @@ 
 #define X86_FEATURE_PVUNLOCK		( 8*32+20) /* "" PV unlock function */
 #define X86_FEATURE_VCPUPREEMPT		( 8*32+21) /* "" PV vcpu_is_preempted function */
 #define X86_FEATURE_TDX_GUEST		( 8*32+22) /* Intel Trust Domain Extensions Guest */
+#define X86_FEATURE_SNP_SECURE_TSC	( 8*32+23) /* "" AMD SNP Secure TSC */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/