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Fri, 16 Feb 2024 16:58:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Adrian Hunter , Alexander Shishkin , Alexandre Ghiti , Andrew Jones , Anup Patel , Arnaldo Carvalho de Melo , Atish Patra , Christian Brauner , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Conor Dooley , devicetree@vger.kernel.org, Evan Green , Guo Ren , Heiko Stuebner , Ian Rogers , Ingo Molnar , James Clark , Jing Zhang , Jiri Olsa , Ji Sheng Teoh , John Garry , Jonathan Corbet , Kan Liang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Ley Foon Tan , linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Namhyung Kim , Palmer Dabbelt , Paul Walmsley , Peter Zijlstra , Rob Herring , Samuel Holland , Weilin Wang , Will Deacon , kaiwenxue1@gmail.com, Yang Jihong Subject: [PATCH RFC 07/20] RISC-V: Add Ssccfg ISA extension definition and parsing Date: Fri, 16 Feb 2024 16:57:25 -0800 Message-Id: <20240217005738.3744121-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240217005738.3744121-1-atishp@rivosinc.com> References: <20240217005738.3744121-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Ssccfg (‘Ss’ for Privileged architecture and Supervisor-level extension, ‘ccfg’ for Counter Configuration) provides access to delegated counters and new supervisor-level state. This patch just enables the definitions and enable parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 44df259cc815..5f4401e221ee 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,8 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_SSCSRIND 74 #define RISCV_ISA_EXT_SMCSRIND 75 +#define RISCV_ISA_EXT_SSCCFG 76 +#define RISCV_ISA_EXT_SMCDELEG 77 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 52ec88dfb004..77cc5dbd73bf 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -300,10 +300,12 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), + __RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),