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Tue, 20 Feb 2024 03:51:05 -0800 From: To: , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v19 1/3] vfio/pci: rename and export do_io_rw() Date: Tue, 20 Feb 2024 17:20:53 +0530 Message-ID: <20240220115055.23546-2-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240220115055.23546-1-ankita@nvidia.com> References: <20240220115055.23546-1-ankita@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|CH2PR12MB4326:EE_ X-MS-Office365-Filtering-Correlation-Id: 3142ab28-c97b-435f-07cf-08dc320a4460 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MCZhJwkQLw21wbJsOyI5OaN9hxBmbqEFJDQXQvtUh+lhgKK6Fiu7Xi2bwtcJqaVN+LWYmpZUp/dMfQUiBWDtXzuGUUxCYr6YGedz66HoFGlU+gW7H5SsT6x/K7KCb+4PslD7nWDjcEqze9VNdwHfijAGiV3nzJ9Jr7Xvdwz9kAYaGH4uDEKowH8DFKzpuEchJ3KmTwVr9X35Nj8n3clFcLQNZ/gF7JiynGD3FECfCHCofiy9JfWsDVjelcC635j8DsxYV+B9RFqycHWPZnJDxCEcnOl98OetgNg37ewq2MfrhLe/YKhHJR0q8MvkZphqz3VZ+nMfQjMF9/TTqdrZvDLDZl67xTlgMwEHAs5UgbTJY5xiEg7ZP0UEkWXsfWkW6aJofKh90Cj7gPew0mHbr7qPYyeVtL70Zv0FR2VYxNyP68/bLEhULPrCcr9uc4kg4oLSq9J5rXtpXYFJQ+gDzq4sRU41XQ61lXiq/ZUXskjowkNB/wOYa+HBVUQ8ViBay9oA7K3w30gNxSutwlQqzS2gGUQOZXEvtHAtqZ9NBDXdT5oUm5pNaQGG65jhrPfaJ6UZpWrJwygsxQ37AQ7mnMT/+9ZsbVop0MPV0z/icBqPEwTyvUWmeRj5Vm56xqxhUg/C7snESIww9sguNEl69guICtgK4zZXDaBrnT9cX6w= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(46966006)(40470700004)(921011);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2024 11:51:25.7036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3142ab28-c97b-435f-07cf-08dc320a4460 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4326 From: Ankit Agrawal do_io_rw() is used to read/write to the device MMIO. The grace hopper VFIO PCI variant driver require this functionality to read/write to its memory. Rename this as vfio_pci_core functions and export as GPL. Reviewed-by: Kevin Tian Reviewed-by: Yishai Hadas Signed-off-by: Ankit Agrawal --- drivers/vfio/pci/vfio_pci_rdwr.c | 16 +++++++++------- include/linux/vfio_pci_core.h | 5 ++++- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 07fea08ea8a2..03b8f7ada1ac 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -96,10 +96,10 @@ VFIO_IOREAD(32) * reads with -1. This is intended for handling MSI-X vector tables and * leftover space for ROM BARs. */ -static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, - void __iomem *io, char __user *buf, - loff_t off, size_t count, size_t x_start, - size_t x_end, bool iswrite) +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, + void __iomem *io, char __user *buf, + loff_t off, size_t count, size_t x_start, + size_t x_end, bool iswrite) { ssize_t done = 0; int ret; @@ -201,6 +201,7 @@ static ssize_t do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, return done; } +EXPORT_SYMBOL_GPL(vfio_pci_core_do_io_rw); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar) { @@ -279,8 +280,8 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, x_end = vdev->msix_offset + vdev->msix_size; } - done = do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, - count, x_start, x_end, iswrite); + done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, + count, x_start, x_end, iswrite); if (done >= 0) *ppos += done; @@ -348,7 +349,8 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf, * probing, so we don't currently worry about access in relation * to the memory enable bit in the command register. */ - done = do_io_rw(vdev, false, iomem, buf, off, count, 0, 0, iswrite); + done = vfio_pci_core_do_io_rw(vdev, false, iomem, buf, off, count, + 0, 0, iswrite); vga_put(vdev->pdev, rsrc); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 85e84b92751b..cf9480a31f3e 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -130,7 +130,10 @@ void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev); int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar); pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev, pci_channel_state_t state); - +ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem, + void __iomem *io, char __user *buf, + loff_t off, size_t count, size_t x_start, + size_t x_end, bool iswrite); #define VFIO_IOWRITE_DECLATION(size) \ int vfio_pci_core_iowrite##size(struct vfio_pci_core_device *vdev, \ bool test_mem, u##size val, void __iomem *io);