From patchwork Tue Feb 27 10:32:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13573468 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4F9E138486 for ; Tue, 27 Feb 2024 10:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709029194; cv=none; b=BIm+aIMJQbdszyIy+t7DSAWWT+rVysmvlBG2TL1hKsBGazTdGTmOpww5MLMNhpwbqC3HUuDcUK94BbUUQCfKBNqyTkJm3c0PoGGq3WtnvD89kns6ED5WumWhRa807q3QkiUIDcdQuG8SWmJZ7cnkDIPivpMGlhy43L1BPbLft4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709029194; c=relaxed/simple; bh=JmFuea6YEZYtRR9sXzEGMQAAFtD5BRLPf0ozY0WPMXk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F/1+9UVZDPf54TviLEFy91Lyh96B6LVsjsqPLkmQiPjseWwfYNVDFBeUJMm05+1j89HifLKbTkOrC8rQ6QpTU2KnQcnJYitVQn7imfekzB3RQmBQJTR5SweGDz1huo3IH/r9BfzseU94mki695HqO/VkOUCsGGEUqCw5FLBsniA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Dwroq3SA; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Dwroq3SA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709029193; x=1740565193; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JmFuea6YEZYtRR9sXzEGMQAAFtD5BRLPf0ozY0WPMXk=; b=Dwroq3SA0eUN+Ume7lZ0t8sT4DISPKzPv8NnViaKEdk1TUcms31FX2CJ vrlbRE8lYN6fG5wXIqHQmh18eX71TJSObHzbmoPLGgiRd49K8+UYI8wuS jKpQoIz0YfrMFBaP737NJBp6XEYBI5X/F8Egf8q1C2qgBy4Z+qUfmN8uk JKDXKK3E5Z4rHT0xMXJSYOaWYrqSUnKw/bGKR42RKIQJhtm+mVNWBzp6t QPz7UPpzM2+GzyrveZu08SdwXaueaySlsIscD5qQ1bGn5HOrk7moW4I4L nuY5lLVvXQKO2pqx1dI2Vbae8jn3MhwRLQvGf2SLTD4LVUJ0dxew6IITE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="6310349" X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6310349" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2024 02:19:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6954903" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa010.fm.intel.com with ESMTP; 27 Feb 2024 02:19:48 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v9 12/21] i386: Introduce module level cpu topology to CPUX86State Date: Tue, 27 Feb 2024 18:32:22 +0800 Message-Id: <20240227103231.1556302-13-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> References: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu Intel CPUs implement module level on hybrid client products (e.g., ADL-N, MTL, etc) and E-core server products. A module contains a set of cores that share certain resources (in current products, the resource usually includes L2 cache, as well as module scoped features and MSRs). Module level support is the prerequisite for L2 cache topology on module level. With module level, we can implement the Guest's CPU topology and future cache topology to be consistent with the Host's on Intel hybrid client/E-core server platforms. Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu --- Changes since v7: * Mapped x86 module to smp module instead of cluster. * Re-wrote the commit message to explain the reason why we needs module level. * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v1: * The background of the introduction of the "cluster" parameter and its exact meaning were revised according to Yanan's explanation. (Yanan) --- hw/i386/x86.c | 5 +++++ target/i386/cpu.c | 1 + target/i386/cpu.h | 3 +++ 3 files changed, 9 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 1e4ff7188f6a..4f91538aaf5d 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -313,6 +313,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, init_topo_info(&topo_info, x86ms); + if (ms->smp.modules > 1) { + env->nr_modules = ms->smp.modules; + /* TODO: Expose module level in CPUID[0x1F]. */ + } + if (ms->smp.dies > 1) { env->nr_dies = ms->smp.dies; set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b0f171c6a465..d2b9298faf14 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7712,6 +7712,7 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) { CPUX86State *env = &cpu->env; + env->nr_modules = 1; env->nr_dies = 1; /* SMT, core and package levels are set by default. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4a55fef1feea..375d63d05ed2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1899,6 +1899,9 @@ typedef struct CPUArchState { /* Number of dies within this CPU package. */ unsigned nr_dies; + /* Number of modules within one die. */ + unsigned nr_modules; + /* Bitmap of available CPU topology levels for this CPU. */ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); } CPUX86State;