From patchwork Tue Feb 27 10:32:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13573477 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EE4F1384B0 for ; Tue, 27 Feb 2024 10:20:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709029238; cv=none; b=N1I5dDLGQDsopktIwo9ajyT+e4ykjt9vVZUfuT7LdRSVuU0d9ifcTfevrwnMqfAMxqZ4GtYCTSgh1glpIbNzLxX8IkSd+dNCuAqFqXcBky/K81tMNZm0KaNQQ6mz6HZK38c5Y6mfMyQkSo0kyQczrwkkrjpwIRADt9JESOHBtsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709029238; c=relaxed/simple; bh=51yZIIBumqpl0Pci1JIC2Mbj/bgzNe6l2iPevAtFhp0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ojyOLOo4t91BcfzIrTnB8g82Uck2anCuqPaneiZyLsdVDGxEvNwgTHGBnTP242ll1H0e6suGgn5iA8Y61/Y4N+ZaVFm3FerLx6UMIw/fNH0i/hBfffBfK21r3+D26iHwwOWuIan1IOq1mNZVnqCpFk+QkJrBK5d7Qf/xgJiLJV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=O+BhxgPu; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="O+BhxgPu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709029237; x=1740565237; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=51yZIIBumqpl0Pci1JIC2Mbj/bgzNe6l2iPevAtFhp0=; b=O+BhxgPu3jrqzEInx7gbRqid6zEm07MgQlLDL+n48gVcHN9T1v9Yfg9K WheEJew5LptoVo5TFmhwy0DpwdDpGmpLNK5+SJDzR4U/PmU7TW/e0DQ7l UWaYQHP0i/tWAIZtiYWtx29ERQskaMsLfVMMGhPYwxSzsC7iFx6FipaVA NLrVdZ4jdPxfL/1oE+V+7rcb6PvqpEuKN+GoukcuAuoFFVE/9yM8s3DFv RtKLmf60vInx71ixGyu92Dbs6jWLfSpcgsn7ahwFzeE7NHb/9miUjH0Vb NCqOMwl801t4Kq4QZbt4fbBN7xbj664gJ8II5Jmd1OZpCh3Fn+ubGghiF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="6310500" X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6310500" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2024 02:20:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,187,1705392000"; d="scan'208";a="6955300" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa010.fm.intel.com with ESMTP; 27 Feb 2024 02:20:32 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v9 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Tue, 27 Feb 2024 18:32:31 +0800 Message-Id: <20240227103231.1556302-22-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> References: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical processors sharing cache. The number of logical processors sharing this cache is NumSharingCache + 1. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Cc: Babu Moger Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Reviewed-by: Babu Moger --- Changes since v7: * Renamed max_processor_ids_for_cache() to max_thread_ids_for_cache(). * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v3: * Explained what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit message. (Babu) Changes since v1: * Used cache->share_level as the parameter in max_processor_ids_for_cache(). --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 07cd729c3524..bc21c2d537b3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -481,20 +481,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t num_sharing_cache; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level == 3) { - num_sharing_cache = 1 << apicid_die_offset(topo_info); - } else { - num_sharing_cache = 1 << apicid_core_offset(topo_info); - } - *eax |= (num_sharing_cache - 1) << 14; + *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);