| Message ID | 20240229010130.1380926-3-atishp@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand |
On 29/02/2024 02:01, Atish Patra wrote: > SBI v2.0 added another function to SBI PMU extension to read > the upper bits of a counter with width larger than XLEN. > > Add the definition for that function. > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > arch/riscv/include/asm/sbi.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 6e68f8dff76b..ef8311dafb91 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { > SBI_EXT_PMU_COUNTER_START, > SBI_EXT_PMU_COUNTER_STOP, > SBI_EXT_PMU_COUNTER_FW_READ, > + SBI_EXT_PMU_COUNTER_FW_READ_HI, > }; > > union sbi_pmu_ctr_info { Reviewed-by: Clément Léger <cleger@rivosinc.com> Thanks, Clément
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6e68f8dff76b..ef8311dafb91 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_START, SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, }; union sbi_pmu_ctr_info {