From patchwork Thu Feb 29 06:36:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13576542 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DEF34595A for ; Thu, 29 Feb 2024 06:39:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709188787; cv=none; b=TIgFqTNCxrCOutGepKVPB6V/3xbbvsQ5ZQhm6IThr8cBK7SSXQmVSM90IUA/+lhtYLqvxZ+Naq2b/OSVS3Df5ljDdNtC3p5iO7H24N/k6tAbRipLf+u7FfeHNqWr0jH3lhJEvxnMiENZFiX3gSPe8qdAiGcIYviUeNfy51MpBMA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709188787; c=relaxed/simple; bh=g4714Yv4cXmBnyaQtDRzn4l5S3H1KPYgRgd3UCmt7rk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NFT95l9D2EznZcBodRCvQJpVNrdJQ9yNi7K4fdZD2rqOUcaYtXEKROnTwc7ibc0sO6DMvTfyAK8s30C/cs4/aQRFnwGjCB5Gbzn3uAnVixwV1LyEKevWjM4ZgC/u1QCIY4KjFmv4mT3pQffgBEOQwGNVNYNtxziYjRcCHmdL1+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EYbAjnt2; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EYbAjnt2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709188786; x=1740724786; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g4714Yv4cXmBnyaQtDRzn4l5S3H1KPYgRgd3UCmt7rk=; b=EYbAjnt2LlbHQiU1+9IWSa3QR42tVede1kcMpBRpBqhp+zdqAnxqDpdk gU9lL3y1tkTucRCw5KTPLLtKAL84mShFN/A2rsq+xyJUbN7EjmC1Fh930 b+U5wWXU/oRG01mdvESqN9XfovNvDk2ICeQF/lQhdBc+yJC1VdKkH0EeO 5NjUxisKgWZMf2T8fVm/T6tjP4hFPYpY6KVmG9EtFHEBukhXdiUZzjXWV zouBMEYBQfRhnkZxXuiLnVk56X2NteUTtHahiJ2F/46V8fHZD0huYXjRW Pg/tYu5zEz2JbUIIYw1aWoyluzwLsDvZi/kAC3CIg6oQTeaqn99lIKMhS Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10998"; a="3802667" X-IronPort-AV: E=Sophos;i="6.06,192,1705392000"; d="scan'208";a="3802667" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 22:39:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,192,1705392000"; d="scan'208";a="8075350" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa007.jf.intel.com with ESMTP; 28 Feb 2024 22:39:39 -0800 From: Xiaoyao Li To: Paolo Bonzini , David Hildenbrand , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , Richard Henderson , Ani Sinha , Peter Xu , Cornelia Huck , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: kvm@vger.kernel.org, qemu-devel@nongnu.org, Michael Roth , Claudio Fontana , Gerd Hoffmann , Isaku Yamahata , Chenyi Qiang , xiaoyao.li@intel.com Subject: [PATCH v5 20/65] i386/tdx: Integrate tdx_caps->xfam_fixed0/1 into tdx_cpuid_lookup Date: Thu, 29 Feb 2024 01:36:41 -0500 Message-Id: <20240229063726.610065-21-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229063726.610065-1-xiaoyao.li@intel.com> References: <20240229063726.610065-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 KVM requires userspace to pass XFAM configuration via CPUID 0xD leaves. Convert tdx_caps->xfam_fixed0/1 into corresponding tdx_cpuid_lookup[].tdx_fixed0/1 field of CPUID 0xD leaves. Thus the requirement can be applied naturally. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 3 --- target/i386/cpu.h | 3 +++ target/i386/kvm/tdx.c | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2666ef380891..b5f0c1080c34 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1576,9 +1576,6 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { }; #undef REGISTER -/* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) - ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { [XSTATE_FP_BIT] = { /* x87 FP state component is always enabled if XSAVE is supported */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7bd604f802a1..782aba921bd5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -595,6 +595,9 @@ typedef enum X86Seg { XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \ XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK) +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 424c0f3c0fbb..24475e6b312e 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -407,6 +407,30 @@ static void update_tdx_cpuid_lookup_by_tdx_caps(void) entry->tdx_fixed0 &= ~config; entry->tdx_fixed1 &= ~config; } + + /* + * Because KVM gets XFAM settings via CPUID leaves 0xD, map + * tdx_caps->xfam_fixed{0, 1} into tdx_cpuid_lookup[].tdx_fixed{0, 1}. + * + * Then the enforment applies in tdx_get_configurable_cpuid() naturally. + */ + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_LO].tdx_fixed0 = + (uint32_t)~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XCR0_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_LO].tdx_fixed1 = + (uint32_t)tdx_caps->xfam_fixed1 & CPUID_XSTATE_XCR0_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_HI].tdx_fixed0 = + (~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XCR0_MASK) >> 32; + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_HI].tdx_fixed1 = + (tdx_caps->xfam_fixed1 & CPUID_XSTATE_XCR0_MASK) >> 32; + + tdx_cpuid_lookup[FEAT_XSAVE_XSS_LO].tdx_fixed0 = + (uint32_t)~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XSS_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XSS_LO].tdx_fixed1 = + (uint32_t)tdx_caps->xfam_fixed1 & CPUID_XSTATE_XSS_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XSS_HI].tdx_fixed0 = + (~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XSS_MASK) >> 32; + tdx_cpuid_lookup[FEAT_XSAVE_XSS_HI].tdx_fixed1 = + (tdx_caps->xfam_fixed1 & CPUID_XSTATE_XSS_MASK) >> 32; } static int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp)