From patchwork Thu Feb 29 06:36:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13576549 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EA2F4C619 for ; Thu, 29 Feb 2024 06:40:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709188833; cv=none; b=PDP4uoKyxlMQutxBFLyTV+K2CG5QGxjwYTrKu9h78Aa6yEnQWk9rfCfRZkoFYJWfyRJXZGCS/ozR2ezBAYkTvRq1xWBUomH6WgGGgh9raXEE+D8t8zfzqOaaLpKPBXzuMZhw+n62AzYgL/GdnA4n+2eBLJ+OX2qHv/XYiEAxzF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709188833; c=relaxed/simple; bh=Gvq++bXmo93zAUhJsRjiDraEH3cCNX+uGjQb5aw6CGM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uwbpIlFbHO/Aq4K/Mi3yTCSmFYzoHzK/lr1ksO7a06um0gpgqvrqnjQTBof62dZknVPZYBhEY6/LuGWoUYUGKrmPmr7UKItOQoHYm6F4gHwlg+qy6+1uy5BQ/x4L4BkJTqoR9hoIDK8XgLvplohdk+dmfXBuKAOpZO0Gdc+2wpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lS/RdaN3; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lS/RdaN3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709188832; x=1740724832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gvq++bXmo93zAUhJsRjiDraEH3cCNX+uGjQb5aw6CGM=; b=lS/RdaN3dZgSnk+vjQBuZD6B3m2/+y0lWDWHMz1bEVqEqywOku/vraFG egITpK/cTjaYzLECpGSRcdTL7HuTI2j2Lle8C3Mw0L0BTHrx7ijTlDNV5 B4638ibqU04XMKb5wGf4k9ftPFkCFncPMr5+h6rk93ioIPlXpz8pn/quc hO4JAeV0Yn7y5MWUhdREtuZjbre0+JpJLsXG7aySH9pPgVM4/KBUdPuZ/ xUTmzcNwzNzixKMCmv1B9dXo1sbVRupu/eDSOHZAifSOGPssZZhukGdi5 MxiBqT2M2yQYjsME5XV2fNyShr9liGfHvQudRU6HPgcRdJwb3oSdgZS1p Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10998"; a="3802772" X-IronPort-AV: E=Sophos;i="6.06,192,1705392000"; d="scan'208";a="3802772" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 22:40:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,192,1705392000"; d="scan'208";a="8075530" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa007.jf.intel.com with ESMTP; 28 Feb 2024 22:40:25 -0800 From: Xiaoyao Li To: Paolo Bonzini , David Hildenbrand , Igor Mammedov , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , Richard Henderson , Ani Sinha , Peter Xu , Cornelia Huck , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: kvm@vger.kernel.org, qemu-devel@nongnu.org, Michael Roth , Claudio Fontana , Gerd Hoffmann , Isaku Yamahata , Chenyi Qiang , xiaoyao.li@intel.com Subject: [PATCH v5 27/65] i386/tdx: Wire CPU features up with attributes of TD guest Date: Thu, 29 Feb 2024 01:36:48 -0500 Message-Id: <20240229063726.610065-28-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229063726.610065-1-xiaoyao.li@intel.com> References: <20240229063726.610065-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For QEMU VMs, PKS is configured via CPUID_7_0_ECX_PKS and PMU is configured by x86cpu->enable_pmu. Reuse the existing configuration interface for TDX VMs. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- target/i386/kvm/tdx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index b6295a644566..262e86fd2c67 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -33,6 +33,8 @@ (1U << KVM_FEATURE_MSI_EXT_DEST_ID)) #define TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE BIT_ULL(28) +#define TDX_TD_ATTRIBUTES_PKS BIT_ULL(30) +#define TDX_TD_ATTRIBUTES_PERFMON BIT_ULL(63) #define TDX_ATTRIBUTES_MAX_BITS 64 @@ -477,6 +479,15 @@ static int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) return 0; } +static void setup_td_guest_attributes(X86CPU *x86cpu) +{ + CPUX86State *env = &x86cpu->env; + + tdx_guest->attributes |= (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS) ? + TDX_TD_ATTRIBUTES_PKS : 0; + tdx_guest->attributes |= x86cpu->enable_pmu ? TDX_TD_ATTRIBUTES_PERFMON : 0; +} + int tdx_pre_create_vcpu(CPUState *cpu, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -499,6 +510,8 @@ int tdx_pre_create_vcpu(CPUState *cpu, Error **errp) return r; } + setup_td_guest_attributes(x86cpu); + init_vm->cpuid.nent = kvm_x86_arch_cpuid(env, init_vm->cpuid.entries, 0); init_vm->attributes = tdx_guest->attributes;