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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099DA.mail.protection.outlook.com (10.167.17.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7362.11 via Frontend Transport; Fri, 1 Mar 2024 07:50:29 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 1 Mar 2024 01:50:20 -0600 From: Sandipan Das To: , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH] KVM: x86/svm/pmu: Set PerfMonV2 global control bits correctly Date: Fri, 1 Mar 2024 13:20:07 +0530 Message-ID: <20240301075007.644152-1-sandipan.das@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DA:EE_|CY8PR12MB8338:EE_ X-MS-Office365-Filtering-Correlation-Id: 077ac97f-fabb-4953-abcd-08dc39c443bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 07:50:29.0951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 077ac97f-fabb-4953-abcd-08dc39c443bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8338 With PerfMonV2, a performance monitoring counter will start operating only when both the PERF_CTLx enable bit as well as the corresponding PerfCntrGlobalCtl enable bit are set. When the PerfMonV2 CPUID feature bit (leaf 0x80000022 EAX bit 0) is set for a guest but the guest kernel does not support PerfMonV2 (such as kernels older than v5.19), the guest counters do not count since the PerfCntrGlobalCtl MSR is initialized to zero and the guest kernel never writes to it. This is not observed on bare-metal as the default value of the PerfCntrGlobalCtl MSR after a reset is 0x3f (assuming there are six counters) and the counters can still be operated by using the enable bit in the PERF_CTLx MSRs. Replicate the same behaviour in guests for compatibility with older kernels. Before: $ perf stat -e cycles:u true Performance counter stats for 'true': 0 cycles:u 0.001074773 seconds time elapsed 0.001169000 seconds user 0.000000000 seconds sys After: $ perf stat -e cycles:u true Performance counter stats for 'true': 227,850 cycles:u 0.037770758 seconds time elapsed 0.000000000 seconds user 0.037886000 seconds sys Reported-by: Babu Moger Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support") Signed-off-by: Sandipan Das Reported-by: Reported-by: Babu Moger Signed-off-by: Sean Christopherson Tested-by: Sandipan Das --- arch/x86/kvm/svm/pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index b6a7ad4d6914..14709c564d6a 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -205,6 +205,7 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) if (pmu->version > 1) { pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); pmu->global_status_mask = pmu->global_ctrl_mask; + pmu->global_ctrl = ~pmu->global_ctrl_mask; } pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;