| Message ID | 20240309012725.1409949-8-seanjc@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/cpu: KVM: Clean up PAT and VMX macros | expand |
On Fri, Mar 08, 2024 at 05:27:23PM -0800, Sean Christopherson wrote: > Date: Fri, 8 Mar 2024 17:27:23 -0800 > From: Sean Christopherson <seanjc@google.com> > Subject: [PATCH v6 7/9] KVM VMX: Move MSR_IA32_VMX_MISC bit defines to > asm/vmx.h > X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog > > Move the handful of MSR_IA32_VMX_MISC bit defines that are currently in > msr-indx.h to vmx.h so that all of the VMX_MISC defines and wrappers can > be found in a single location. > > Opportunistically use BIT_ULL() instead of open coding hex values, add > defines for feature bits that are architectural defined, and move the > defines down in the file so that they are colocated with the helpers for > getting fields from VMX_MISC. > > No functional change intended. > > Cc: Shan Kang <shan.kang@intel.com> > Cc: Kai Huang <kai.huang@intel.com> > Signed-off-by: Xin Li <xin3.li@intel.com> > [sean: split to separate patch, write changelog] > Signed-off-by: Sean Christopherson <seanjc@google.com> > --- > arch/x86/include/asm/msr-index.h | 5 ----- > arch/x86/include/asm/vmx.h | 19 ++++++++++++------- > arch/x86/kvm/vmx/capabilities.h | 4 ++-- > arch/x86/kvm/vmx/nested.c | 2 +- > arch/x86/kvm/vmx/nested.h | 2 +- > 5 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 5ca81ad509b5..3531856def3d 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -1138,11 +1138,6 @@ > #define MSR_IA32_SMBA_BW_BASE 0xc0000280 > #define MSR_IA32_EVT_CFG_BASE 0xc0000400 > > -/* MSR_IA32_VMX_MISC bits */ > -#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) > -#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) > -#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F > - > /* AMD-V MSRs */ > #define MSR_VM_CR 0xc0010114 > #define MSR_VM_IGNNE 0xc0010115 > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index ce6d166fc3c5..6ff179b11235 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -120,13 +120,6 @@ > > #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff > > -#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f > -#define VMX_MISC_SAVE_EFER_LMA 0x00000020 > -#define VMX_MISC_ACTIVITY_HLT 0x00000040 > -#define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100 > -#define VMX_MISC_ZERO_LEN_INS 0x40000000 > -#define VMX_MISC_MSR_LIST_MULTIPLIER 512 > - > /* VMFUNC functions */ > #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28) > > @@ -155,6 +148,18 @@ static inline u32 vmx_basic_vmcs_mem_type(u64 vmx_basic) > return (vmx_basic & GENMASK_ULL(53, 50)) >> 50; > } > > +#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK GENMASK_ULL(4, 0) > +#define VMX_MISC_SAVE_EFER_LMA BIT_ULL(5) > +#define VMX_MISC_ACTIVITY_HLT BIT_ULL(6) > +#define VMX_MISC_ACTIVITY_SHUTDOWN BIT_ULL(7) > +#define VMX_MISC_ACTIVITY_WAIT_SIPI BIT_ULL(8) > +#define VMX_MISC_INTEL_PT BIT_ULL(14) > +#define VMX_MISC_RDMSR_IN_SMM BIT_ULL(15) > +#define VMX_MISC_VMXOFF_BLOCK_SMI BIT_ULL(28) > +#define VMX_MISC_VMWRITE_SHADOW_RO_FIELDS BIT_ULL(29) > +#define VMX_MISC_ZERO_LEN_INS BIT_ULL(30) > +#define VMX_MISC_MSR_LIST_MULTIPLIER 512 > + Maybe it's better to mention this patch also define some new bits: * VMX_MISC_ACTIVITY_SHUTDOWN * VMX_MISC_RDMSR_IN_SMM * VMX_MISC_VMXOFF_BLOCK_SMI Otherwise, Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
On Fri, 2024-03-08 at 17:27 -0800, Sean Christopherson wrote: > Move the handful of MSR_IA32_VMX_MISC bit defines that are currently in > msr-indx.h to vmx.h so that all of the VMX_MISC defines and wrappers can > be found in a single location. > > Opportunistically use BIT_ULL() instead of open coding hex values, add > defines for feature bits that are architectural defined, and move the > defines down in the file so that they are colocated with the helpers for > getting fields from VMX_MISC. > > No functional change intended. > > Cc: Shan Kang <shan.kang@intel.com> > Cc: Kai Huang <kai.huang@intel.com> > Signed-off-by: Xin Li <xin3.li@intel.com> > [sean: split to separate patch, write changelog] > Signed-off-by: Sean Christopherson <seanjc@google.com> > Reviewed-by: Kai Huang <kai.huang@intel.com>
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 5ca81ad509b5..3531856def3d 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1138,11 +1138,6 @@ #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 -/* MSR_IA32_VMX_MISC bits */ -#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) -#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) -#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F - /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 #define MSR_VM_IGNNE 0xc0010115 diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index ce6d166fc3c5..6ff179b11235 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -120,13 +120,6 @@ #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff -#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f -#define VMX_MISC_SAVE_EFER_LMA 0x00000020 -#define VMX_MISC_ACTIVITY_HLT 0x00000040 -#define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100 -#define VMX_MISC_ZERO_LEN_INS 0x40000000 -#define VMX_MISC_MSR_LIST_MULTIPLIER 512 - /* VMFUNC functions */ #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28) @@ -155,6 +148,18 @@ static inline u32 vmx_basic_vmcs_mem_type(u64 vmx_basic) return (vmx_basic & GENMASK_ULL(53, 50)) >> 50; } +#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK GENMASK_ULL(4, 0) +#define VMX_MISC_SAVE_EFER_LMA BIT_ULL(5) +#define VMX_MISC_ACTIVITY_HLT BIT_ULL(6) +#define VMX_MISC_ACTIVITY_SHUTDOWN BIT_ULL(7) +#define VMX_MISC_ACTIVITY_WAIT_SIPI BIT_ULL(8) +#define VMX_MISC_INTEL_PT BIT_ULL(14) +#define VMX_MISC_RDMSR_IN_SMM BIT_ULL(15) +#define VMX_MISC_VMXOFF_BLOCK_SMI BIT_ULL(28) +#define VMX_MISC_VMWRITE_SHADOW_RO_FIELDS BIT_ULL(29) +#define VMX_MISC_ZERO_LEN_INS BIT_ULL(30) +#define VMX_MISC_MSR_LIST_MULTIPLIER 512 + static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc) { return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index 86ce8bb96bed..cb6588238f46 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -223,7 +223,7 @@ static inline bool cpu_has_vmx_vmfunc(void) static inline bool cpu_has_vmx_shadow_vmcs(void) { /* check if the cpu supports writing r/o exit information fields */ - if (!(vmcs_config.misc & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) + if (!(vmcs_config.misc & VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) return false; return vmcs_config.cpu_based_2nd_exec_ctrl & @@ -365,7 +365,7 @@ static inline bool cpu_has_vmx_invvpid_global(void) static inline bool cpu_has_vmx_intel_pt(void) { - return (vmcs_config.misc & MSR_IA32_VMX_MISC_INTEL_PT) && + return (vmcs_config.misc & VMX_MISC_INTEL_PT) && (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) && (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL); } diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 4ad8696c25af..06512ee7a5c4 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -6998,7 +6998,7 @@ static void nested_vmx_setup_misc_data(struct vmcs_config *vmcs_conf, { msrs->misc_low = (u32)vmcs_conf->misc & VMX_MISC_SAVE_EFER_LMA; msrs->misc_low |= - MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS | + VMX_MISC_VMWRITE_SHADOW_RO_FIELDS | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | VMX_MISC_ACTIVITY_HLT | VMX_MISC_ACTIVITY_WAIT_SIPI; diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index cce4e2aa30fb..0782fe599757 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -109,7 +109,7 @@ static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu) { return to_vmx(vcpu)->nested.msrs.misc_low & - MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; + VMX_MISC_VMWRITE_SHADOW_RO_FIELDS; } static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)