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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000066ED.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Mon, 25 Mar 2024 21:36:58 +0000 Received: from ethanolx16dchost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Mar 2024 16:36:57 -0500 From: Pavan Kumar Paluri To: CC: , , , , , , Pavan Kumar Paluri Subject: [kvm-unit-tests RFC PATCH 3/3] x86 AMD SEV-ES: Setup a new page table and install level 1 PTEs Date: Mon, 25 Mar 2024 16:36:23 -0500 Message-ID: <20240325213623.747590-3-papaluri@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240325213623.747590-1-papaluri@amd.com> References: <20240325213623.747590-1-papaluri@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|SN7PR12MB6792:EE_ X-MS-Office365-Filtering-Correlation-Id: c32ff007-aef5-4f7c-441a-08dc4d13b36f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Mar 2024 21:36:58.8492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c32ff007-aef5-4f7c-441a-08dc4d13b36f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6792 KUT's UEFI tests don't currently have support for page allocation. SEV-ES/SNP tests will need this later, so the support for page allocation is provided via setup_vm(). SEV-ES/SNP guest uses GHCB page to communicate with the host. Such a page should remain unencrypted (its c-bit should be unset). Therefore, call setup_ghcb_pte() in the path of setup_vm() to make sure c-bit of GHCB's pte is unset. Signed-off-by: Pavan Kumar Paluri --- lib/x86/vm.c | 6 ++++++ x86/amd_sev.c | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index 90f73fbb2dfd..ce2063aee75d 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -3,6 +3,7 @@ #include "vmalloc.h" #include "alloc_page.h" #include "smp.h" +#include "amd_sev.h" static pteval_t pte_opt_mask; @@ -197,6 +198,11 @@ void *setup_mmu(phys_addr_t end_of_memory, void *opt_mask) init_alloc_vpage((void*)(3ul << 30)); #endif +#ifdef CONFIG_EFI + if (amd_sev_es_enabled()) + setup_ghcb_pte(cr3); +#endif + write_cr3(virt_to_phys(cr3)); #ifndef __x86_64__ write_cr4(X86_CR4_PSE); diff --git a/x86/amd_sev.c b/x86/amd_sev.c index 7757d4f85b7a..03636e581dfe 100644 --- a/x86/amd_sev.c +++ b/x86/amd_sev.c @@ -14,6 +14,8 @@ #include "x86/processor.h" #include "x86/amd_sev.h" #include "msr.h" +#include "x86/vm.h" +#include "alloc_page.h" #define EXIT_SUCCESS 0 #define EXIT_FAILURE 1 @@ -89,9 +91,14 @@ static void test_stringio(void) int main(void) { int rtn; + unsigned long *vaddr; rtn = test_sev_activation(); report(rtn == EXIT_SUCCESS, "SEV activation test."); test_sev_es_activation(); test_stringio(); + setup_vm(); + vaddr = alloc_page(); + if (!vaddr) + assert_msg(vaddr, "Page allocation Failure"); return report_summary(); }