| Message ID | 20240329-dev-maxh-lin-452-6-9-v1-1-1534f93b94a7@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: support Sdtrig extension hcontext/scontext CSRs | expand |
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..47d82cd35ca7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -121,6 +121,13 @@ properties: version of the privileged ISA specification. # multi-letter extensions, sorted alphanumerically + - const: sdtrig + description: | + The standard Sdtrig extension for introduce trigger CSRs for + cause a breakpoint exception, entry into Debug Mode, + or trace action as frozen at commit 359bedc ("Freeze Candidate") + of riscv-debug-spec + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced
As riscv-debug-spec [1] Chapter 5 introduce Sdtrig extension. Add an entry for the Sdtrig extension to the riscv,isa-extensions property. Link: https://github.com/riscv/riscv-debug-spec/releases/download/ar20231208/riscv-debug-stable.pdf [1] Signed-off-by: Max Hsu <max.hsu@sifive.com> --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+)