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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:43 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:17 +0800 Subject: [PATCH RFC 01/11] dt-bindings: riscv: Add Sdtrig ISA extension Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-1-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 As riscv-debug-spec [1] Chapter 5 introduce Sdtrig extension. Add an entry for the Sdtrig extension to the riscv,isa-extensions property. Link: https://github.com/riscv/riscv-debug-spec/releases/download/ar20231208/riscv-debug-stable.pdf [1] Signed-off-by: Max Hsu --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..47d82cd35ca7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -121,6 +121,13 @@ properties: version of the privileged ISA specification. # multi-letter extensions, sorted alphanumerically + - const: sdtrig + description: | + The standard Sdtrig extension for introduce trigger CSRs for + cause a breakpoint exception, entry into Debug Mode, + or trace action as frozen at commit 359bedc ("Freeze Candidate") + of riscv-debug-spec + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced