[v6,10/24] RISC-V: KVM: Fix the initial sample period value

Message ID	20240411000752.955910-11-atishp@rivosinc.com (mailing list archive)
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Headers	show Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A371D529 for <kvm@vger.kernel.org>; Thu, 11 Apr 2024 00:08:34 +0000 (UTC) From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Alexey Makhalov <alexey.amakhalov@broadcom.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v6 10/24] RISC-V: KVM: Fix the initial sample period value Date: Wed, 10 Apr 2024 17:07:38 -0700 Message-Id: <20240411000752.955910-11-atishp@rivosinc.com> In-Reply-To: <20240411000752.955910-1-atishp@rivosinc.com> References: <20240411000752.955910-1-atishp@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| expand [v6,00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v6,01/24] RISC-V: Fix the typo in Scountovf CSR name [v6,02/24] RISC-V: Add FIRMWARE_READ_HI definition [v6,03/24] drivers/perf: riscv: Read upper bits of a firmware counter [v6,04/24] drivers/perf: riscv: Use BIT macro for shifting operations [v6,05/24] RISC-V: Add SBI PMU snapshot definitions [v6,06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name [v6,07/24] RISC-V: Use the minor version mask while computing sbi version [v6,08/24] drivers/perf: riscv: Implement SBI PMU snapshot function [v6,09/24] drivers/perf: riscv: Fix counter mask iteration for RV32 [v6,10/24] RISC-V: KVM: Fix the initial sample period value [v6,11/24] RISC-V: KVM: No need to update the counter value during reset [v6,12/24] RISC-V: KVM: No need to exit to the user space if perf event failed [v6,13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature [v6,14/24] RISC-V: KVM: Add perf sampling support for guests [v6,15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 [v6,16/24] RISC-V: KVM: Improve firmware counter read function [v6,17/24] KVM: riscv: selftests: Move sbi definitions to its own header file [v6,18/24] KVM: riscv: selftests: Add helper functions for extension checks [v6,19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test [v6,20/24] KVM: riscv: selftests: Add SBI PMU extension definitions [v6,21/24] KVM: riscv: selftests: Add SBI PMU selftest [v6,22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality [v6,23/24] KVM: riscv: selftests: Add a test for counter overflow [v6,24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test

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20240411000752.955910-11-atishp@rivosinc.com (mailing list archive)

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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Ajay Kaher <ajay.kaher@broadcom.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Alexey Makhalov <alexey.amakhalov@broadcom.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Juergen Gross <jgross@suse.com>,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org,
	linux-kselftest@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Shuah Khan <shuah@kernel.org>,
	virtualization@lists.linux.dev,
	Will Deacon <will@kernel.org>,
	x86@kernel.org
Subject: [PATCH v6 10/24] RISC-V: KVM: Fix the initial sample period value
Date: Wed, 10 Apr 2024 17:07:38 -0700
Message-Id: <20240411000752.955910-11-atishp@rivosinc.com>
In-Reply-To: <20240411000752.955910-1-atishp@rivosinc.com>
References: <20240411000752.955910-1-atishp@rivosinc.com>
Precedence: bulk
MIME-Version: 1.0
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Series

RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand

Commit Message

Atish Patra April 11, 2024, 12:07 a.m. UTC

The initial sample period value when counter value is not assigned
should be set to maximum value supported by the counter width.
Otherwise, it may result in spurious interrupts.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kvm/vcpu_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
index 86391a5061dd..cee1b9ca4ec4 100644
--- a/arch/riscv/kvm/vcpu_pmu.c
+++ b/arch/riscv/kvm/vcpu_pmu.c
@@ -39,7 +39,7 @@  static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc)
 	u64 sample_period;
 
 	if (!pmc->counter_val)
-		sample_period = counter_val_mask + 1;
+		sample_period = counter_val_mask;
 	else
 		sample_period = (-pmc->counter_val) & counter_val_mask;

[v6,10/24] RISC-V: KVM: Fix the initial sample period value

Commit Message

Patch