[v7,02/24] RISC-V: Add FIRMWARE_READ_HI definition

Message ID	20240416184421.3693802-3-atishp@rivosinc.com (mailing list archive)
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Headers	show Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE16413777B for <kvm@vger.kernel.org>; Tue, 16 Apr 2024 18:44:44 +0000 (UTC) From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v7 02/24] RISC-V: Add FIRMWARE_READ_HI definition Date: Tue, 16 Apr 2024 11:43:59 -0700 Message-Id: <20240416184421.3693802-3-atishp@rivosinc.com> In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com> References: <20240416184421.3693802-1-atishp@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| expand [v7,00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v7,01/24] RISC-V: Fix the typo in Scountovf CSR name [v7,02/24] RISC-V: Add FIRMWARE_READ_HI definition [v7,03/24] drivers/perf: riscv: Read upper bits of a firmware counter [v7,04/24] drivers/perf: riscv: Use BIT macro for shifting operations [v7,05/24] RISC-V: Add SBI PMU snapshot definitions [v7,06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name [v7,07/24] RISC-V: Use the minor version mask while computing sbi version [v7,08/24] drivers/perf: riscv: Implement SBI PMU snapshot function [v7,09/24] drivers/perf: riscv: Fix counter mask iteration for RV32 [v7,10/24] RISC-V: KVM: Fix the initial sample period value [v7,11/24] RISC-V: KVM: No need to update the counter value during reset [v7,12/24] RISC-V: KVM: No need to exit to the user space if perf event failed [v7,13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature [v7,14/24] RISC-V: KVM: Add perf sampling support for guests [v7,15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 [v7,16/24] RISC-V: KVM: Improve firmware counter read function [v7,17/24] KVM: riscv: selftests: Move sbi definitions to its own header file [v7,18/24] KVM: riscv: selftests: Add helper functions for extension checks [v7,19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test [v7,20/24] KVM: riscv: selftests: Add SBI PMU extension definitions [v7,21/24] KVM: riscv: selftests: Add SBI PMU selftest [v7,22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality [v7,23/24] KVM: riscv: selftests: Add a test for counter overflow [v7,24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test

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20240416184421.3693802-3-atishp@rivosinc.com (mailing list archive)

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New

Headers

From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>,
	=?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>,
 Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>,
 Ajay Kaher <ajay.kaher@broadcom.com>, Albert Ou <aou@eecs.berkeley.edu>,
 Alexandre Ghiti <alexghiti@rivosinc.com>, Juergen Gross <jgross@suse.com>,
 kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
 linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org,
 Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>,
 Paolo Bonzini <pbonzini@redhat.com>,
 Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>,
 virtualization@lists.linux.dev, Will Deacon <will@kernel.org>, x86@kernel.org
Subject: [PATCH v7 02/24] RISC-V: Add FIRMWARE_READ_HI definition
Date: Tue, 16 Apr 2024 11:43:59 -0700
Message-Id: <20240416184421.3693802-3-atishp@rivosinc.com>
In-Reply-To: <20240416184421.3693802-1-atishp@rivosinc.com>
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Series

RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand

Commit Message

Atish Patra April 16, 2024, 6:43 p.m. UTC

SBI v2.0 added another function to SBI PMU extension to read
the upper bits of a counter with width larger than XLEN.

Add the definition for that function.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/sbi.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 6e68f8dff76b..ef8311dafb91 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -131,6 +131,7 @@  enum sbi_ext_pmu_fid {
 	SBI_EXT_PMU_COUNTER_START,
 	SBI_EXT_PMU_COUNTER_STOP,
 	SBI_EXT_PMU_COUNTER_FW_READ,
+	SBI_EXT_PMU_COUNTER_FW_READ_HI,
 };
 
 union sbi_pmu_ctr_info {

[v7,02/24] RISC-V: Add FIRMWARE_READ_HI definition

Commit Message

Patch