From patchwork Wed Apr 24 15:49:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13642081 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89FC81635DD for ; Wed, 24 Apr 2024 15:37:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713973061; cv=none; b=JYQqULpKMe72/DBFd6KZKNJ1vNpXG+hCe2435n76ExXOk2o+1lpq040hOItLQtrlnuGvKnpzJ2JaS6sRbraAR0h5I6gw8cLsQm3QIKAVGDirdxpokGsT/s+wfirVPfIvuLrYjm88eEGcJqXlMXSkNFx9wXcmdySteGB4CwCzdQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713973061; c=relaxed/simple; bh=OlYKuDPPHSu3h5BsrEeYzI1MeMMYvSAts1dW6DU/vTY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=faGaC+qjyUWgZ3WlzPbmio2XukXDaCWIQAkFKRX4InotlL4wSEta/Vs+HPfRprhSVgc5V2uHa4Zehyesg0U6ev1V2bOaaHp+mgVA4TCK3brXebcTExCIZL9DiJ67WQr/8oKKGixccl1xrU8MIHlhiIFIbwRFPVtPddAriIq9m8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cvyzqtv9; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cvyzqtv9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713973060; x=1745509060; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OlYKuDPPHSu3h5BsrEeYzI1MeMMYvSAts1dW6DU/vTY=; b=cvyzqtv96ktQa8JskNvOwo07+fVQp9c+v935+zfu9jM8AcDGDER58FFQ GVpwJPReMmtdlzp/cB+U5EzxRah3p6E9VNQqZIYRnNBlKCM4lvh+FNzQY 2hhdTE7ex+pA4PBnCXmbNHPimGycd6klrEzgE3vARBMWxPAmkyQvx/nFP UnRdj7onYAIkRfI9L5wgTlStU14hbAWSyWVlqWuqeDBqiV0A7/Z3A8Yx7 du2SrXY/JILdL6iJvH50/QsWz8goX535e3vNWZw9c6DKhYk0pu111Y/7M sr+bE1/HnhjUqej5G/RpR1E5h9Xb8aJRc3y3lDXkibG7+4OBB5d2jrdsk g==; X-CSE-ConnectionGUID: RzW0fp72QiqkA/vnFCMb1Q== X-CSE-MsgGUID: oFyBq7stRvWbEQr81DgnLw== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="12545859" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="12545859" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 08:37:39 -0700 X-CSE-ConnectionGUID: XXNVp/cPSSarPdr4uQB0CA== X-CSE-MsgGUID: UveUyuf9THWITkMsV4ys6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="25363356" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orviesa008.jf.intel.com with ESMTP; 24 Apr 2024 08:37:35 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Xiaoyao Li , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH v11 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Wed, 24 Apr 2024 23:49:29 +0800 Message-Id: <20240424154929.1487382-22-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424154929.1487382-1-zhao1.liu@intel.com> References: <20240424154929.1487382-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical processors sharing cache. The number of logical processors sharing this cache is NumSharingCache + 1. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Reviewed-by: Babu Moger --- Changes since v7: * Renamed max_processor_ids_for_cache() to max_thread_ids_for_cache(). * Dropped Michael/Babu's ACKed/Tested tags since the code change. * Re-added Yongwei's Tested tag For his re-testing. Changes since v3: * Explained what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit message. (Babu) Changes since v1: * Used cache->share_level as the parameter in max_processor_ids_for_cache(). --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6ab517a59aee..369c5ee54fa6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -478,20 +478,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t num_sharing_cache; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level == 3) { - num_sharing_cache = 1 << apicid_die_offset(topo_info); - } else { - num_sharing_cache = 1 << apicid_core_offset(topo_info); - } - *eax |= (num_sharing_cache - 1) << 14; + *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);