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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id b16-20020a056a000a9000b006f4473daa38sm3480068pfl.128.2024.05.04.05.29.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 May 2024 05:29:32 -0700 (PDT) From: Nicholas Piggin To: Thomas Huth Cc: Nicholas Piggin , Laurent Vivier , Andrew Jones , linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org Subject: [kvm-unit-tests PATCH v9 11/31] powerpc/sprs: Test hypervisor registers on powernv machine Date: Sat, 4 May 2024 22:28:17 +1000 Message-ID: <20240504122841.1177683-12-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240504122841.1177683-1-npiggin@gmail.com> References: <20240504122841.1177683-1-npiggin@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This enables HV privilege registers to be tested with the powernv machine. Acked-by: Thomas Huth Signed-off-by: Nicholas Piggin --- powerpc/sprs.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/powerpc/sprs.c b/powerpc/sprs.c index c25dac1f6..de9e87a21 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = { [190] = { "HFSCR", 64, HV_RW, }, [256] = { "VRSAVE", 32, RW, }, [259] = { "SPRG3", 64, RO, }, -[284] = { "TBL", 32, HV_WO, }, -[285] = { "TBU", 32, HV_WO, }, -[286] = { "TBU40", 64, HV_WO, }, +[284] = { "TBL", 32, HV_WO, }, /* Things can go a bit wonky with */ +[285] = { "TBU", 32, HV_WO, }, /* Timebase changing. Should save */ +[286] = { "TBU40", 64, HV_WO, }, /* and restore it. */ [304] = { "HSPRG0", 64, HV_RW, }, [305] = { "HSPRG1", 64, HV_RW, }, [306] = { "HDSISR", 32, HV_RW, SPR_INT, }, [307] = { "HDAR", 64, HV_RW, SPR_INT, }, [308] = { "SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, [309] = { "PURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, -[313] = { "HRMOR", 64, HV_RW, }, +[313] = { "HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */ [314] = { "HSRR0", 64, HV_RW, SPR_INT, }, [315] = { "HSRR1", 64, HV_RW, SPR_INT, }, [318] = { "LPCR", 64, HV_RW, }, @@ -306,7 +306,7 @@ static const struct spr sprs_power9_10[1024] = { [921] = { "TSCR", 32, HV_RW, }, [922] = { "TTR", 64, HV_RW, }, [1006]= { "TRACE", 64, WO, }, -[1008]= { "HID", 64, HV_RW, }, +[1008]= { "HID", 64, HV_RW, SPR_HARNESS, }, /* HILE would be unhelpful to change */ }; /* This covers POWER8 and POWER9 PMUs */ @@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = { static struct spr sprs[1024]; +static bool spr_read_perms(int spr) +{ + if (cpu_has_hv) + return !!(sprs[spr].access & SPR_HV_READ); + else + return !!(sprs[spr].access & SPR_OS_READ); +} + +static bool spr_write_perms(int spr) +{ + if (cpu_has_hv) + return !!(sprs[spr].access & SPR_HV_WRITE); + else + return !!(sprs[spr].access & SPR_OS_WRITE); +} + static void setup_sprs(void) { int i; @@ -461,7 +477,7 @@ static void get_sprs(uint64_t *v) int i; for (i = 0; i < 1024; i++) { - if (!(sprs[i].access & SPR_OS_READ)) + if (!spr_read_perms(i)) continue; v[i] = __mfspr(i); } @@ -472,8 +488,9 @@ static void set_sprs(uint64_t val) int i; for (i = 0; i < 1024; i++) { - if (!(sprs[i].access & SPR_OS_WRITE)) + if (!spr_write_perms(i)) continue; + if (sprs[i].type & SPR_HARNESS) continue; __mtspr(i, val); @@ -561,7 +578,7 @@ int main(int argc, char **argv) for (i = 0; i < 1024; i++) { bool pass = true; - if (!(sprs[i].access & SPR_OS_READ)) + if (!spr_read_perms(i)) continue; if (sprs[i].width == 32) {