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b=aYpgs8mA17ngkRa+5QsxiwIidp+A4qwUMfFQv4JFglsKSXh3vMpEJmBxqzNRWQ5Jt2 JGgmP1blB+g67Dx3aLwlYEldK/bxFqH+TzryMFaOMWWqp/WJVqQy8gyaWisJZTsPaXAP 0kG7j1ND5Jj8i21ge1LubCJI7XMlnKxf1FTV27ZYFDuYBxsXoWTVm3Ymeq4vcZU+gQco SJYuDPUUyDf9XgGeHpOL2JJJjmggP+9Y7vvSGgSnAcjxayAx3+tjVYmM+sMNFXVXh2YT BwjEU2dIBsBn4vouYSErFMAhgwVYCZurIq0H/cgMZL9byLUfpPtVTgip5+/UcpiWFIxT CmqA== X-Forwarded-Encrypted: i=1; AJvYcCWQKYRRwcjSUQI5K/lmYekNhBOO45Y4+0C2s74HrmpOGMu+xRq2Jcvvh3UnJxoIoZlKIk+OYYqP6q4h+W1402Gwby03 X-Gm-Message-State: AOJu0YwpJkya05YRonSDSmLga9zUVGYusZy6Dg7DCjPWflGG10zUoAx7 U6YTyf+S2lITIY4dRrJsJhh3RGnAkDPjcktHOEJ6knZpmbg5jUC2ixxNiaJVOLLLFLCbFJdXfH/ LJ6ImJw== X-Google-Smtp-Source: AGHT+IH/aio6aXzh0G0m07C5bH+IQw4PQz3caZp9wzBjKH6yC8WEliTQJXEqK9SnOaJKMY888p+zuWu6ZYu+ X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a0d:ea44:0:b0:618:4a14:54b8 with SMTP id t65-20020a0dea44000000b006184a1454b8mr2124323ywe.1.1714973458211; Sun, 05 May 2024 22:30:58 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:29:42 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-18-mizhang@google.com> Subject: [PATCH v2 17/54] KVM: x86/pmu: Always set global enable bits in passthrough mode From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das Currently, the global control bits for a vcpu are restored to the reset state only if the guest PMU version is less than 2. This works for emulated PMU as the MSRs are intercepted and backing events are created for and managed by the host PMU [1]. If such a guest in run with passthrough PMU, the counters no longer work because the global enable bits are cleared. Hence, set the global enable bits to their reset state if passthrough PMU is used. A passthrough-capable host may not necessarily support PMU version 2 and it can choose to restore or save the global control state from struct kvm_pmu in the PMU context save and restore helpers depending on the availability of the global control register. [1] 7b46b733bdb4 ("KVM: x86/pmu: Set enable bits for GP counters in PERF_GLOBAL_CTRL at "RESET""); Reported-by: Mingwei Zhang Signed-off-by: Sandipan Das [removed the fixes tag] --- arch/x86/kvm/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 5768ea2935e9..e656f72fdace 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -787,7 +787,7 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu) * in the global controls). Emulate that behavior when refreshing the * PMU so that userspace doesn't need to manually set PERF_GLOBAL_CTRL. */ - if (kvm_pmu_has_perf_global_ctrl(pmu) && pmu->nr_arch_gp_counters) + if ((pmu->passthrough || kvm_pmu_has_perf_global_ctrl(pmu)) && pmu->nr_arch_gp_counters) pmu->global_ctrl = GENMASK_ULL(pmu->nr_arch_gp_counters - 1, 0); }