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b=iFPzvjefDRNFyQ94Ny0Hcg6nZBJEw8wHdwObXX+IXwOhyyQh80CtxXb39jq0U+ZVpI GtoITXwZ6+TGhMUv2QExm6PFmzR4aCg0lGLmfR9VI+nNqzjqRS1DFSv3X/AjK/IDruUk vL/E0bpWHYq8z7u+rwJ1iEjqlH5pV9eI9GqOlzwhl6X8lg60OFioShrc5yZEa8KDXrVk 619fXa6E66gZwS22SPPguhM74mpOpJfANIpILTqmFIfSzZTk5pe+Wvc9aKTiQpYL7h0e FEBapQ5QCMcLxYYc7KEZkC3zfr9CekddGkNIHRThJoxhlWnN0FyjA9CV5uA6EDWtlDY/ LXOg== X-Forwarded-Encrypted: i=1; AJvYcCXwATUNYoZm8Q0vMlQRW8P7suHyM4569djJgI444EAKhKJZJLIlUC6mH3tZOIWbtdNW3PyN2TmHnxWRrFvzl2JXLDF5 X-Gm-Message-State: AOJu0YyPiSiNiWX0ouRUnNsr8TPyYDTnakxMYaZGzDBdPx/WzdtHAbp2 NhKRf3fS4e2vX+wh7AnlNtXbNWk0QW93Ff/3CoR46Jlq5Z1txHZM2oPYpQROBQMd9ymeqHU8paH Fze32rg== X-Google-Smtp-Source: AGHT+IEhOZv1p1zs3TnUGO6lf+4CykGiPpB1mkJ4IsXZPJGzL/4mqaPmD0EEMS34GHaQzHMnj1shCFO74F8d X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a0d:d90d:0:b0:61b:14af:df5 with SMTP id b13-20020a0dd90d000000b0061b14af0df5mr2514160ywe.10.1714973432656; Sun, 05 May 2024 22:30:32 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:29:28 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-4-mizhang@google.com> Subject: [PATCH v2 03/54] KVM: x86/pmu: Do not mask LVTPC when handling a PMI on AMD platforms From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das On AMD and Hygon platforms, the local APIC does not automatically set the mask bit of the LVTPC register when handling a PMI and there is no need to clear it in the kernel's PMI handler. For guests, the mask bit is currently set by kvm_apic_local_deliver() and unless it is cleared by the guest kernel's PMI handler, PMIs stop arriving and break use-cases like sampling with perf record. This does not affect non-PerfMonV2 guests because PMIs are handled in the guest kernel by x86_pmu_handle_irq() which always clears the LVTPC mask bit irrespective of the vendor. Before: $ perf record -e cycles:u true [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.001 MB perf.data (1 samples) ] After: $ perf record -e cycles:u true [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.002 MB perf.data (19 samples) ] Fixes: a16eb25b09c0 ("KVM: x86: Mask LVTPC when handling a PMI") Cc: stable@vger.kernel.org Signed-off-by: Sandipan Das Reviewed-by: Jim Mattson [sean: use is_intel_compatible instead of !is_amd_or_hygon()] Signed-off-by: Sean Christopherson Message-ID: <20240405235603.1173076-3-seanjc@google.com> Signed-off-by: Paolo Bonzini --- arch/x86/kvm/lapic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index cf37586f0466..ebf41023be38 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2776,7 +2776,8 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL); - if (r && lvt_type == APIC_LVTPC) + if (r && lvt_type == APIC_LVTPC && + guest_cpuid_is_intel_compatible(apic->vcpu)) kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED); return r; }