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AJvYcCXjgXmhcxt6tz6KtmgTdFzTviVtL64T+T/LJ9zx9wzpmAw9rFw6mKLzw6YyXgUvtTUNI2OriJCsPyI2os/bm4pNDn4z X-Gm-Message-State: AOJu0Yy++4MbUTk+gq8u5fOFQZwIGIgvjs+c2R59GU9GnXRcgnudOiPL Cg2TjAWg2v6p5gV1z1mQHBLvAkyWy1pIW3WGFtGvXKU/f2kWeNzomMqedm7GdHgvqjxd+2/7P+m I6Ck+Kg== X-Google-Smtp-Source: AGHT+IFYp8coMMMQBNCwd97fczYgJy2ue1P30RZll3cvaIcmpsrwWSW7fDCLCClAJjUuBkJxelFlX0RornAO X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a17:90a:9f91:b0:2b0:73ac:ff38 with SMTP id o17-20020a17090a9f9100b002b073acff38mr25441pjp.1.1714973521086; Sun, 05 May 2024 22:32:01 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 6 May 2024 05:30:15 +0000 In-Reply-To: <20240506053020.3911940-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240506053020.3911940-1-mizhang@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240506053020.3911940-51-mizhang@google.com> Subject: [PATCH v2 50/54] KVM: x86/pmu/svm: Implement callback to disable MSR interception From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das Implement the AMD-specific callback for passthrough PMU that disables interception of PMU-related MSRs if the guest PMU counters qualify the requirement of passthrough. The PMU registers include the following. - PerfCntrGlobalStatus (MSR 0xc0000300) - PerfCntrGlobalCtl (MSR 0xc0000301) - PerfCntrGlobalStatusClr (MSR 0xc0000302) - PerfCntrGlobalStatusSet (MSR 0xc0000303) - PERF_CTLx and PERF_CTRx pairs (MSRs 0xc0010200..0xc001020b) Note that the passthrough/interception is invoked after each CPUID set. Since CPUID set can be done multiple times, do the intercept/clear of the bitmap explicitly for each counters as well as global registers. Signed-off-by: Sandipan Das --- arch/x86/kvm/svm/pmu.c | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 385478103f65..2ad62b8ac2c2 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -247,6 +247,49 @@ static bool amd_is_rdpmc_passthru_allowed(struct kvm_vcpu *vcpu) return true; } +static void amd_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct vcpu_svm *svm = to_svm(vcpu); + int msr_clear = !!(is_passthrough_pmu_enabled(vcpu)); + int i; + + for (i = 0; i < kvm_pmu_cap.num_counters_gp; i++) { + /* + * PERF_CTLx registers require interception in order to clear + * HostOnly bit and set GuestOnly bit. This is to prevent the + * PERF_CTRx registers from counting before VM entry and after + * VM exit. + */ + set_msr_interception(vcpu, svm->msrpm, MSR_F15H_PERF_CTL + 2 * i, 0, 0); + + /* + * Pass through counters exposed to the guest and intercept + * counters that are unexposed. Do this explicitly since this + * function may be set multiple times before vcpu runs. + */ + if (i >= pmu->nr_arch_gp_counters) + msr_clear = 0; + set_msr_interception(vcpu, svm->msrpm, MSR_F15H_PERF_CTR + 2 * i, msr_clear, msr_clear); + } + + /* + * In mediated passthrough vPMU, intercept global PMU MSRs when guest + * PMU only owns a subset of counters provided in HW or its version is + * less than 2. + */ + if (is_passthrough_pmu_enabled(vcpu) && pmu->version > 1 && + pmu->nr_arch_gp_counters == kvm_pmu_cap.num_counters_gp) + msr_clear = 1; + else + msr_clear = 0; + + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, msr_clear, msr_clear); + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, msr_clear, msr_clear); + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, msr_clear, msr_clear); + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, msr_clear, msr_clear); +} + struct kvm_pmu_ops amd_pmu_ops __initdata = { .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = amd_msr_idx_to_pmc, @@ -257,6 +300,7 @@ struct kvm_pmu_ops amd_pmu_ops __initdata = { .refresh = amd_pmu_refresh, .init = amd_pmu_init, .is_rdpmc_passthru_allowed = amd_is_rdpmc_passthru_allowed, + .passthrough_pmu_msrs = amd_passthrough_pmu_msrs, .EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_AMD_PMC_MAX_GENERIC, .MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS,