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AJvYcCWra1nsbHhjw0JpY6/L1ae/txhB7WQDkIh0nOKGVdM+AKh/UnZWac+WEzMCQzkOco6QajZ7+IV9HMQBIAXG97O8Jc/m X-Gm-Message-State: AOJu0YyR351vYPGZOByIWJeIv1MQldZUIgAiqInIVheFx2vCQgva5hlU J7t8oM05pYz4Fb6QGcDUBtzDnk/JNHJrg8x1dq+b8oeZlXgjuXZ1ipTRi+EO5CI= X-Google-Smtp-Source: AGHT+IGq5go7pjxVXZoiDIctGP4OrpbOzSdrxavQVhZcrfZhYA5v6u0JB+p8JidVC79uF/koqWAkCw== X-Received: by 2002:a17:906:ae8f:b0:a66:ebc8:ad2c with SMTP id a640c23a62f3a-a66ebd812e1mr100669966b.42.1717098171713; Thu, 30 May 2024 12:42:51 -0700 (PDT) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a67e73faa76sm8314766b.75.2024.05.30.12.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 12:42:51 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id A25505F8D5; Thu, 30 May 2024 20:42:50 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , Cameron Esfahani , Alexandre Iooss , Yanan Wang , Paolo Bonzini , Eduardo Habkost , Sunil Muthuswamy , Richard Henderson , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Mahmoud Mandour , Reinoud Zandijk , =?utf-8?q?Alex_Benn=C3=A9e?= , kvm@vger.kernel.org, Roman Bolshakov Subject: [PATCH 1/5] hw/core: expand on the alignment of CPUState Date: Thu, 30 May 2024 20:42:46 +0100 Message-Id: <20240530194250.1801701-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240530194250.1801701-1-alex.bennee@linaro.org> References: <20240530194250.1801701-1-alex.bennee@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make the relationship between CPUState, ArchCPU and cpu_env a bit clearer in the kdoc comments. Signed-off-by: Alex Bennée Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bb398e8237..35d345371b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -391,7 +391,8 @@ struct qemu_work_item; #define CPU_UNSET_NUMA_NODE_ID -1 /** - * CPUState: + * struct CPUState - common state of one CPU core or thread. + * * @cpu_index: CPU index (informative). * @cluster_index: Identifies which cluster this CPU is in. * For boards which don't define clusters or for "loose" CPUs not assigned @@ -439,10 +440,15 @@ struct qemu_work_item; * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU * dirty ring structure. * - * State of one CPU core or thread. + * @neg_align: The CPUState is the common part of a concrete ArchCPU + * which is allocated when an individual CPU instance is created. As + * such care is taken is ensure there is no gap between between + * CPUState and CPUArchState within ArchCPU. * - * Align, in order to match possible alignment required by CPUArchState, - * and eliminate a hole between CPUState and CPUArchState within ArchCPU. + * @neg: The architectural register state ("cpu_env") immediately follows CPUState + * in ArchCPU and is passed to TCG code. The @neg structure holds some + * common TCG CPU variables which are accessed with a negative offset + * from cpu_env. */ struct CPUState { /*< private >*/