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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c7b0besm6969413a91.14.2024.07.28.09.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jul 2024 09:50:33 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH v5 2/5] riscv: Update exception cause list Date: Mon, 29 Jul 2024 00:50:19 +0800 Message-ID: <20240728165022.30075-3-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240728165022.30075-1-jamestiotio@gmail.com> References: <20240728165022.30075-1-jamestiotio@gmail.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the list of exception and interrupt causes to follow the latest RISC-V privileged ISA specification (version 20240411 section 18.6.1). Reviewed-by: Andrew Jones Signed-off-by: James Raphael Tiovalen --- lib/riscv/asm/csr.h | 10 ++++++++++ lib/riscv/asm/processor.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h index d6909d93..ba810c9f 100644 --- a/lib/riscv/asm/csr.h +++ b/lib/riscv/asm/csr.h @@ -36,6 +36,16 @@ #define EXC_VIRTUAL_INST_FAULT 22 #define EXC_STORE_GUEST_PAGE_FAULT 23 +/* Interrupt causes */ +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h index 6451adb5..4c9ad968 100644 --- a/lib/riscv/asm/processor.h +++ b/lib/riscv/asm/processor.h @@ -4,7 +4,7 @@ #include #include -#define EXCEPTION_CAUSE_MAX 16 +#define EXCEPTION_CAUSE_MAX 24 #define INTERRUPT_CAUSE_MAX 16 typedef void (*exception_fn)(struct pt_regs *);