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b=DOHrca9eC1IhEDfoTD4nHxmuCZRIzRtAtP8aI0DdRwj95120bhGh15OMIO4KKLx86Z 6eaLYjoCWZWw42pIpT4XihLzXpnkAJZ8ENgF1bxrs3tC4w46V13weVr5GVi+dZ1VsPqY 2L13PYzs3/5wOL4Erx87eFkRmY4MvBmkHHHu0t3+oDWRGOskasTjIg1g4D99qiB4JGAa MxwhTlN7KC04A1QUxjcOEwGCvnCSpp5vuYUL0YEkxdnOC2CX2e4H+ZRCtzx7RD5mm/wP SVvAw9+/1OEZmbU6OYmePkxahWx5lilzgDmq4WaDElI5CYHMwMSUC2OylkpI933mtEaE VbxA== X-Forwarded-Encrypted: i=1; AJvYcCUkI5Lk7o3fLt3mWP4ZGyaVAWH+9CH8dgNezMyWE/HNjhu5FrwcMTgBL3kUstu4X2YXrlO8ds9s4mBUVUv4V5+mlbZJ X-Gm-Message-State: AOJu0YzFTKP1LD4GaYYu9udDmes1MKxiBgHzYqtrXaAiqEP3bOXSvywq b/y/yzQ4bpbQQkeY0TusnKwnwnOIPldiJYiXgQLZqHG7QMdtTxKo5PIjzp4lpW92rUfNlpE9Zdg FtlOaOw== X-Google-Smtp-Source: AGHT+IGPMFisB/nCQ2SpyxPF79PtrHunowCmHj93kJuiBDB6BwR2q9YvSxx59YdpinxgM55/oSsQQokOOaXz X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a05:6a00:858d:b0:70e:9e1b:b76c with SMTP id d2e1a72fcca58-7105d6d1e06mr20445b3a.2.1722488406318; Wed, 31 Jul 2024 22:00:06 -0700 (PDT) Reply-To: Mingwei Zhang Date: Thu, 1 Aug 2024 04:58:39 +0000 In-Reply-To: <20240801045907.4010984-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> X-Mailer: git-send-email 2.46.0.rc1.232.g9752f9e123-goog Message-ID: <20240801045907.4010984-31-mizhang@google.com> Subject: [RFC PATCH v3 30/58] KVM: x86/pmu: Exclude PMU MSRs in vmx_get_passthrough_msr_slot() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Reject PMU MSRs interception explicitly in vmx_get_passthrough_msr_slot() since interception of PMU MSRs are specially handled in intel_passthrough_pmu_msrs(). Signed-off-by: Mingwei Zhang Signed-off-by: Dapeng Mi Tested-by: Yongwei Ma --- arch/x86/kvm/vmx/vmx.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 34a420fa98c5..41102658ed21 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -166,7 +166,7 @@ module_param(enable_passthrough_pmu, bool, 0444); /* * List of MSRs that can be directly passed to the guest. - * In addition to these x2apic, PT and LBR MSRs are handled specially. + * In addition to these x2apic, PMU, PT and LBR MSRs are handled specially. */ static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_PASSTHROUGH_MSRS] = { MSR_IA32_SPEC_CTRL, @@ -695,6 +695,13 @@ static int vmx_get_passthrough_msr_slot(u32 msr) case MSR_LBR_CORE_FROM ... MSR_LBR_CORE_FROM + 8: case MSR_LBR_CORE_TO ... MSR_LBR_CORE_TO + 8: /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */ + case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + 7: + case MSR_IA32_PERFCTR0 ... MSR_IA32_PERFCTR0 + 7: + case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + 2: + case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_CORE_PERF_GLOBAL_CTRL: + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + /* PMU MSRs. These are handled in intel_passthrough_pmu_msrs() */ return -ENOENT; }