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b=uMHOOGoY28QanQUjOL8il3Y05BLMWI7t8OgVQEAQaFAizs+sH3dOH/dL20x/hJxEx1 cUU6D9IvO7//sRI8mUAYXjehTUA4ovYUx9c9iKQkABhod9DsIYPh6mVGY+3pIW5BGWJl WoboV8p6nfV+tY6rnKvkF+g1SShkktNcYyAcRYGX/Ux+VYe6r5vg582RpKigxYYlNHS1 w/M+jgHrmTWQDR8cxzP5lBS23Wb89B6Zws0GQ4GonaGvBphqsxuzkMW6aJQkbLsyi13k /JHQCDorx0fVHW6uGjwslujxxrgrgBpqL+wskOnqydUC2toPnxH9FPwL+Vvuv6mQEarz VkoQ== X-Forwarded-Encrypted: i=1; AJvYcCVtg7PTWqzt5TGEqlintprM/UTn2Pru/8d5Q8dZOtmWykRyAG2sHsCnMXut+Bkuh9F6hh16yR238Dmk2MYKUAMih5Oc X-Gm-Message-State: AOJu0Yy2C9fY6NdUnEDpnTx85QbKHY4WAMIKPGjwgn4BzHWPx9VwhBmO 43eyi8zL7apKiVW5/UQH+1b0/9IIxFVp8z1F3R2d6IGjFkMrrdXtwPwxDu+u4lveRDxVsXM0yr7 ZCFF4gQ== X-Google-Smtp-Source: AGHT+IHbs8qaJDfvFGAXP/rpBAwEhmqT0IS9EaOILk19416ojQXGwDiYFKRgx0TkGPVP948qxfLhKBzuwVNb X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a05:6a00:9444:b0:70d:2a24:245d with SMTP id d2e1a72fcca58-7105d7d6f05mr6682b3a.3.1722488446062; Wed, 31 Jul 2024 22:00:46 -0700 (PDT) Reply-To: Mingwei Zhang Date: Thu, 1 Aug 2024 04:59:00 +0000 In-Reply-To: <20240801045907.4010984-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> X-Mailer: git-send-email 2.46.0.rc1.232.g9752f9e123-goog Message-ID: <20240801045907.4010984-52-mizhang@google.com> Subject: [RFC PATCH v3 51/58] KVM: x86/pmu/svm: Allow RDPMC pass through when all counters exposed to guest From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das If passthrough PMU is enabled and all counters exposed to guest, clear the RDPMC interception bit in the VMCB Control Area (byte offset 0xc bit 15) to let RDPMC instructions proceed without VM-Exits. This improves the guest PMU performance in passthrough mode. If either condition is not satisfied, then intercept RDPMC and prevent guest accessing unexposed counters. Note that On AMD platforms, passing through RDPMC will only allow guests to read the general-purpose counters. Details about the RDPMC interception bit can be found in Appendix B the "Layout of VMCB" from the AMD64 Architecture Programmer's Manual Volume 2. Signed-off-by: Sandipan Das Signed-off-by: Mingwei Zhang --- arch/x86/kvm/svm/svm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 12868b7e6f51..fc78f34832ca 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1229,6 +1229,11 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) /* No need to intercept these MSRs */ set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); + + if (kvm_pmu_check_rdpmc_passthrough(vcpu)) + svm_clr_intercept(svm, INTERCEPT_RDPMC); + else + svm_set_intercept(svm, INTERCEPT_RDPMC); } }