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b=alWiTnvsn2r0B/Rbt4n+ypAh5qjjO5bZt4etURc/LQlk9yghEYTxqXbjkzYtmrleHn px7qJ9/y/aHbei+Fbv1+QvK4DNJElNBN5WztwHNa23mYyBXcNFvIdqKfXB0se1EYHSFD gEUg6zUlhNQVfHXR+nQGZ5mFQNjYWc21iFlFuHR5IVy7Zys0LRn0KMZ32Jz+umPTuw+G aPZiysDzPJFQ3c5Bz2tr4ksOnZtQit60xsqe//T0g4jilVn8YDlq5WKllCtR0rLlDVx/ Fva9QcGyiZgzR3zcpmDtOm7S3N6ixpLdUK2WXkd+fd3mokCrXyk/ezbLEpLieRFfUoR4 DTcg== X-Forwarded-Encrypted: i=1; AJvYcCUdj4u1PemAICOIarTfktFXri+kW313Rd/L2LR7oBohAZO40uJ5yYEA5bQN/grZrltQC+ltiOL5hJm2i38hSYvDwFX9 X-Gm-Message-State: AOJu0Yx0oU85FKt4OllK/8TxorKNGbX9ng6M2N+t7btvxYbCdLa7uMMf Bis5bTkiwGLcP6+CcfedQceiCUdu8m2aQPtaCPLSTuupW/LLnX0ho/9JOXAsFnY8+gIGJRDqY9W 81QKCzg== X-Google-Smtp-Source: AGHT+IFBlYeU4l8+KBps0mlbqMtbd2Yclwsw8dmK7Kp2BehpNXQf8F5wL2xKaITxDppl5saznX7iR1mMQ22i X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a63:1c47:0:b0:6f3:b24:6c27 with SMTP id 41be03b00d2f7-7b634b58f82mr2706a12.5.1722488449902; Wed, 31 Jul 2024 22:00:49 -0700 (PDT) Reply-To: Mingwei Zhang Date: Thu, 1 Aug 2024 04:59:02 +0000 In-Reply-To: <20240801045907.4010984-1-mizhang@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> X-Mailer: git-send-email 2.46.0.rc1.232.g9752f9e123-goog Message-ID: <20240801045907.4010984-54-mizhang@google.com> Subject: [RFC PATCH v3 53/58] KVM: x86/pmu/svm: Set GuestOnly bit and clear HostOnly bit when guest write to event selectors From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , Mingwei Zhang , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org From: Sandipan Das On AMD platforms, there is no way to restore PerfCntrGlobalCtl at VM-Entry or clear it at VM-Exit. Since the register states will be restored before entering and saved after exiting guest context, the counters can keep ticking and even overflow leading to chaos while still in host context. To avoid this, the PERF_CTLx MSRs (event selectors) are always intercepted. KVM will always set the GuestOnly bit and clear the HostOnly bit so that the counters run only in guest context even if their enable bits are set. Intercepting these MSRs is also necessary for guest event filtering. Signed-off-by: Sandipan Das Signed-off-by: Mingwei Zhang --- arch/x86/kvm/svm/pmu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index cc03c3e9941f..2b7cc7616162 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -165,7 +165,12 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) data &= ~pmu->reserved_bits; if (data != pmc->eventsel) { pmc->eventsel = data; - kvm_pmu_request_counter_reprogram(pmc); + if (is_passthrough_pmu_enabled(vcpu)) { + data &= ~AMD64_EVENTSEL_HOSTONLY; + pmc->eventsel_hw = data | AMD64_EVENTSEL_GUESTONLY; + } else { + kvm_pmu_request_counter_reprogram(pmc); + } } return 0; }